drm/i915: WA: FBC Render Nuke.

WaFbcNukeOn3DBlt for IVB, HSW.

According BSPec: "Workaround: Do not enable Render Command Streamer tracking for FBC.
Instead insert a LRI to address 0x50380 with data 0x00000004 after the PIPE_CONTROL that
follows each render submission."

v2: Chris noticed that flush_domains check was missing here and also suggested to do
    LRI only when fbc is enabled. To avoid do a I915_READ on every flush lets use the
    module parameter check.

v3: Adding Wa name as Damien suggested.

v4: Ville noticed VLV doesn't support fbc at all and comment came wrong from spec.

v5: Ville noticed than on blt a Cache Clean LRI should be used instead the Nuke one.

v6: Check for flush domain on blt (by Ville).
    Check for scanout dirty (by Chris).

v7: Apply proper fbc_dirty implemented by Chris.

v8: remove unused variables.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 29 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0e72da6ad0fa..1ef081cd1706 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -280,6 +280,27 @@ gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
         return 0;
 }
 
+static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
+{
+        int ret;
+
+        if (!ring->fbc_dirty)
+                return 0;
+
+        ret = intel_ring_begin(ring, 4);
+        if (ret)
+                return ret;
+        intel_ring_emit(ring, MI_NOOP);
+        /* WaFbcNukeOn3DBlt:ivb/hsw */
+        intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+        intel_ring_emit(ring, MSG_FBC_REND_STATE);
+        intel_ring_emit(ring, value);
+        intel_ring_advance(ring);
+
+        ring->fbc_dirty = false;
+        return 0;
+}
+
 static int
 gen7_render_ring_flush(struct intel_ring_buffer *ring,
                        u32 invalidate_domains, u32 flush_domains)
@@ -336,6 +357,9 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring,
         intel_ring_emit(ring, 0);
         intel_ring_advance(ring);
 
+        if (flush_domains)
+                return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
+
         return 0;
 }
 
@@ -1685,6 +1709,7 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 static int gen6_ring_flush(struct intel_ring_buffer *ring,
                            u32 invalidate, u32 flush)
 {
+        struct drm_device *dev = ring->dev;
         uint32_t cmd;
         int ret;
 
@@ -1707,6 +1732,10 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
         intel_ring_emit(ring, 0);
         intel_ring_emit(ring, MI_NOOP);
         intel_ring_advance(ring);
+
+        if (IS_GEN7(dev) && flush)
+                return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
+
         return 0;
 }