diff options
author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2013-08-06 17:57:13 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-08-23 08:52:26 -0400 |
commit | edbfdb456053d0738e6b06a3827ead4158bfc918 (patch) | |
tree | d694ee51770617896cb1d940672354efdb4ad48d /drivers/gpu/drm/i915/intel_ringbuffer.c | |
parent | 43eaea131823c5ca13d03364e61bd15f0b22a0f7 (diff) |
drm/i915: wrap GEN6_PMIMR changes
Just like we're doing with the other IMR changes.
One of the functional changes is that not every caller was doing the
POSTING_READ.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2e370804248f..7de29d40d1ad 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c | |||
@@ -1062,10 +1062,8 @@ hsw_vebox_get_irq(struct intel_ring_buffer *ring) | |||
1062 | 1062 | ||
1063 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | 1063 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
1064 | if (ring->irq_refcount++ == 0) { | 1064 | if (ring->irq_refcount++ == 0) { |
1065 | u32 pm_imr = I915_READ(GEN6_PMIMR); | ||
1066 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | 1065 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
1067 | I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask); | 1066 | snb_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
1068 | POSTING_READ(GEN6_PMIMR); | ||
1069 | } | 1067 | } |
1070 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | 1068 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
1071 | 1069 | ||
@@ -1084,10 +1082,8 @@ hsw_vebox_put_irq(struct intel_ring_buffer *ring) | |||
1084 | 1082 | ||
1085 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | 1083 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
1086 | if (--ring->irq_refcount == 0) { | 1084 | if (--ring->irq_refcount == 0) { |
1087 | u32 pm_imr = I915_READ(GEN6_PMIMR); | ||
1088 | I915_WRITE_IMR(ring, ~0); | 1085 | I915_WRITE_IMR(ring, ~0); |
1089 | I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask); | 1086 | snb_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
1090 | POSTING_READ(GEN6_PMIMR); | ||
1091 | } | 1087 | } |
1092 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | 1088 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
1093 | } | 1089 | } |