drm/i915: consolidate interrupt naming scheme

The motivation here is we're going to add some new interrupt definitions
and handling outside of the GT interrupts which is all we've managed so
far (with some RPS exceptions). By consolidating the names in the future
we can make thing a bit cleaner as we don't need to define register
names twice, and we can leverage pretty decent overlap in HW registers
since ILK.

To explain briefly what is in the comments: there are two sets of
interrupt masking/enabling registers. At least so far, the definitions
of the two sets overlap. The old code setup distinct names for
interrupts in each set, ie. one for global, and one for ring. This made
things confusing when using the wrong defines in the wrong places.

rebase: Modified VLV bits

v2: Renamed GT_RENDER_MASTER to GT_RENDER_CS_MASTER (Damien)

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 12 insertions, 9 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c7a89bb051a0..5ab8cc2cafe2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -560,7 +560,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 
         if (HAS_L3_GPU_CACHE(dev))
-                I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
+                I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
 
         return ret;
 }
@@ -982,8 +982,9 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
         if (ring->irq_refcount.gt++ == 0) {
                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
-                        I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
-                                                GEN6_RENDER_L3_PARITY_ERROR));
+                        I915_WRITE_IMR(ring,
+                                       ~(ring->irq_enable_mask |
+                                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
                 else
                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
@@ -1005,7 +1006,8 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
         if (--ring->irq_refcount.gt == 0) {
                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
-                        I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
+                        I915_WRITE_IMR(ring,
+                                       ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
                 else
                         I915_WRITE_IMR(ring, ~0);
                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
@@ -1682,7 +1684,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
                         ring->flush = gen6_render_ring_flush;
                 ring->irq_get = gen6_ring_get_irq;
                 ring->irq_put = gen6_ring_put_irq;
-                ring->irq_enable_mask = GT_USER_INTERRUPT;
+                ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
                 ring->get_seqno = gen6_ring_get_seqno;
                 ring->set_seqno = ring_set_seqno;
                 ring->sync_to = gen6_ring_sync;
@@ -1701,7 +1703,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
                 ring->set_seqno = pc_render_set_seqno;
                 ring->irq_get = gen5_ring_get_irq;
                 ring->irq_put = gen5_ring_put_irq;
-                ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
+                ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
+                                        GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
         } else {
                 ring->add_request = i9xx_add_request;
                 if (INTEL_INFO(dev)->gen < 4)
@@ -1843,7 +1846,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
                 ring->add_request = gen6_add_request;
                 ring->get_seqno = gen6_ring_get_seqno;
                 ring->set_seqno = ring_set_seqno;
-                ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
+                ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
                 ring->irq_get = gen6_ring_get_irq;
                 ring->irq_put = gen6_ring_put_irq;
                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
@@ -1863,7 +1866,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
                 ring->get_seqno = ring_get_seqno;
                 ring->set_seqno = ring_set_seqno;
                 if (IS_GEN5(dev)) {
-                        ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
+                        ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
                         ring->irq_get = gen5_ring_get_irq;
                         ring->irq_put = gen5_ring_put_irq;
                 } else {
@@ -1892,7 +1895,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
         ring->add_request = gen6_add_request;
         ring->get_seqno = gen6_ring_get_seqno;
         ring->set_seqno = ring_set_seqno;
-        ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
+        ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
         ring->irq_get = gen6_ring_get_irq;
         ring->irq_put = gen6_ring_put_irq;
         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;