drm/i915: Convert irq_refounct to struct

It's overkill on older gens, but it's useful for newer gens.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 8 insertions, 8 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 89dfc63677ad..c7a89bb051a0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -795,7 +795,7 @@ gen5_ring_get_irq(struct intel_ring_buffer *ring)
                 return false;
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
-        if (ring->irq_refcount++ == 0) {
+        if (ring->irq_refcount.gt++ == 0) {
                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
                 POSTING_READ(GTIMR);
@@ -813,7 +813,7 @@ gen5_ring_put_irq(struct intel_ring_buffer *ring)
         unsigned long flags;
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
-        if (--ring->irq_refcount == 0) {
+        if (--ring->irq_refcount.gt == 0) {
                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
                 POSTING_READ(GTIMR);
@@ -832,7 +832,7 @@ i9xx_ring_get_irq(struct intel_ring_buffer *ring)
                 return false;
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
-        if (ring->irq_refcount++ == 0) {
+        if (ring->irq_refcount.gt++ == 0) {
                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
                 I915_WRITE(IMR, dev_priv->irq_mask);
                 POSTING_READ(IMR);
@@ -850,7 +850,7 @@ i9xx_ring_put_irq(struct intel_ring_buffer *ring)
         unsigned long flags;
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
-        if (--ring->irq_refcount == 0) {
+        if (--ring->irq_refcount.gt == 0) {
                 dev_priv->irq_mask |= ring->irq_enable_mask;
                 I915_WRITE(IMR, dev_priv->irq_mask);
                 POSTING_READ(IMR);
@@ -869,7 +869,7 @@ i8xx_ring_get_irq(struct intel_ring_buffer *ring)
                 return false;
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
-        if (ring->irq_refcount++ == 0) {
+        if (ring->irq_refcount.gt++ == 0) {
                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
                 I915_WRITE16(IMR, dev_priv->irq_mask);
                 POSTING_READ16(IMR);
@@ -887,7 +887,7 @@ i8xx_ring_put_irq(struct intel_ring_buffer *ring)
         unsigned long flags;
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
-        if (--ring->irq_refcount == 0) {
+        if (--ring->irq_refcount.gt == 0) {
                 dev_priv->irq_mask |= ring->irq_enable_mask;
                 I915_WRITE16(IMR, dev_priv->irq_mask);
                 POSTING_READ16(IMR);
@@ -980,7 +980,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
         gen6_gt_force_wake_get(dev_priv);
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
-        if (ring->irq_refcount++ == 0) {
+        if (ring->irq_refcount.gt++ == 0) {
                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
                         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
                                                 GEN6_RENDER_L3_PARITY_ERROR));
@@ -1003,7 +1003,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
         unsigned long flags;
 
         spin_lock_irqsave(&dev_priv->irq_lock, flags);
-        if (--ring->irq_refcount == 0) {
+        if (--ring->irq_refcount.gt == 0) {
                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
                         I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
                 else