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authorChris Wilson <chris@chris-wilson.co.uk>2014-03-21 13:18:54 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-04-01 16:58:04 -0400
commitaa83e30d8f71c966498f8f7f587514283c47e1b6 (patch)
tree5b28f076a1a09253ed597a872e4a983e18bf7cbc /drivers/gpu/drm/i915/intel_ringbuffer.c
parentc8431fda9f9f3c3b7490cb44bd5720b494a2421e (diff)
drm/i915: Rename GFX_TLB_INVALIDATE_ALWAYS
The documentation calls this GFX_MODE bit "Flush TLB invalidate Mode". However, that is not a good name for an enable bit as it doesn't make it clear what is enabled. An even worse name is GFX_TLB_INVALIDATE_ALWAYS as enabling that bit actually prevents the TLB from being invalidated at every flush. This leads to great confusion when reading code and proposed patches. To get around this try to bake in what is enabled by setting the bit and call it GFX_TLB_INVALIDATE_EXPLICIT. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: "Gupta, Sourab" <sourab.gupta@intel.com> Acked-by: "Gupta, Sourab" <sourab.gupta@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 6bc68bdcf433..64a0ecf970b9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -589,11 +589,11 @@ static int init_render_ring(struct intel_ring_buffer *ring)
589 /* Required for the hardware to program scanline values for waiting */ 589 /* Required for the hardware to program scanline values for waiting */
590 if (INTEL_INFO(dev)->gen == 6) 590 if (INTEL_INFO(dev)->gen == 6)
591 I915_WRITE(GFX_MODE, 591 I915_WRITE(GFX_MODE,
592 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); 592 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
593 593
594 if (IS_GEN7(dev)) 594 if (IS_GEN7(dev))
595 I915_WRITE(GFX_MODE_GEN7, 595 I915_WRITE(GFX_MODE_GEN7,
596 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | 596 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
597 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); 597 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
598 598
599 if (INTEL_INFO(dev)->gen >= 5) { 599 if (INTEL_INFO(dev)->gen >= 5) {
@@ -616,7 +616,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
616 * TODO: consider explicitly setting the bit for GEN5 616 * TODO: consider explicitly setting the bit for GEN5
617 */ 617 */
618 ring->itlb_before_ctx_switch = 618 ring->itlb_before_ctx_switch =
619 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); 619 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_EXPLICIT);
620 } 620 }
621 621
622 if (INTEL_INFO(dev)->gen >= 6) 622 if (INTEL_INFO(dev)->gen >= 6)