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authorDave Airlie <airlied@redhat.com>2013-02-07 21:10:18 -0500
committerDave Airlie <airlied@redhat.com>2013-02-07 21:10:18 -0500
commit6dc1c49da6dd3bf020a66b2a135b9625ac01c2c7 (patch)
tree38a6c5d4896de01449e9d224088ae223161fcd3c /drivers/gpu/drm/i915/intel_ringbuffer.c
parentcd17ef4114ad5c514b17e6a0bb02a309ab90b692 (diff)
parent5845b81bdad374f98f809a658ec747d92c9595c4 (diff)
Merge branch 'fbcon-locking-fixes' of ssh://people.freedesktop.org/~airlied/linux into drm-next
This pulls in most of Linus tree up to -rc6, this fixes the worst lockdep reported issues and re-enables fbcon lockdep. (not the fbcon maintainer) * 'fbcon-locking-fixes' of ssh://people.freedesktop.org/~airlied/linux: (529 commits) Revert "Revert "console: implement lockdep support for console_lock"" fbcon: fix locking harder fb: Yet another band-aid for fixing lockdep mess fb: rework locking to fix lock ordering on takeover
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c24
1 files changed, 18 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index dc6ae2fa1cee..00525ff59045 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -505,13 +505,25 @@ static int init_render_ring(struct intel_ring_buffer *ring)
505 struct drm_i915_private *dev_priv = dev->dev_private; 505 struct drm_i915_private *dev_priv = dev->dev_private;
506 int ret = init_ring_common(ring); 506 int ret = init_ring_common(ring);
507 507
508 if (INTEL_INFO(dev)->gen > 3) { 508 if (INTEL_INFO(dev)->gen > 3)
509 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); 509 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
510 if (IS_GEN7(dev)) 510
511 I915_WRITE(GFX_MODE_GEN7, 511 /* We need to disable the AsyncFlip performance optimisations in order
512 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | 512 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
513 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); 513 * programmed to '1' on all products.
514 } 514 */
515 if (INTEL_INFO(dev)->gen >= 6)
516 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
517
518 /* Required for the hardware to program scanline values for waiting */
519 if (INTEL_INFO(dev)->gen == 6)
520 I915_WRITE(GFX_MODE,
521 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
522
523 if (IS_GEN7(dev))
524 I915_WRITE(GFX_MODE_GEN7,
525 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
526 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
515 527
516 if (INTEL_INFO(dev)->gen >= 5) { 528 if (INTEL_INFO(dev)->gen >= 5) {
517 ret = init_pipe_control(ring); 529 ret = init_pipe_control(ring);