drm/i915: Replace open coded MI_BATCH_GTT

The (2<<6) virtual memory space selector harks back to gen3 and is
mandatory given our use of GTT space for batchbuffers. On gen4+, use of
the GTT became mandatory and bit6 marked reserved. However the code must
now explicitly set (1<<7), which conveniently is also (2<<6).

To clarify the meaning for future readers, replace the open coded (2<<6)
with MI_BATCH_GTT.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 3 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 492812db537b..4ae651bb1c97 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -786,7 +786,8 @@ i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
                 return ret;
 
         intel_ring_emit(ring,
-                        MI_BATCH_BUFFER_START | (2 << 6) |
+                        MI_BATCH_BUFFER_START |
+                        MI_BATCH_GTT |
                         MI_BATCH_NON_SECURE_I965);
         intel_ring_emit(ring, offset);
         intel_ring_advance(ring);
@@ -823,7 +824,7 @@ i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
         if (ret)
                 return ret;
 
-        intel_ring_emit(ring, MI_BATCH_BUFFER_START | (2 << 6));
+        intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
         intel_ring_advance(ring);