drm/i915: kill dev_priv->rps.lock

Now that the rps interrupt locking isn't clearly separated (at elast
conceptually) from all the other interrupt locking having a different
lock stopped making sense: It protects much more than just the rps
workqueue it started out with. But with the addition of VECS the
separation started to blurr and resulted in some more complex locking
for the ring interrupt refcount.

With this we can (again) unifiy the ringbuffer irq refcounts without
causing a massive confusion, but that's for the next patch.

v2: Explain better why the rps.lock once made sense and why no longer,
requested by Ben.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 4 insertions, 4 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 54495df2403e..33a74a803008 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1055,14 +1055,14 @@ hsw_vebox_get_irq(struct intel_ring_buffer *ring)
         if (!dev->irq_enabled)
                 return false;
 
-        spin_lock_irqsave(&dev_priv->rps.lock, flags);
+        spin_lock_irqsave(&dev_priv->irq_lock, flags);
         if (ring->irq_refcount.pm++ == 0) {
                 u32 pm_imr = I915_READ(GEN6_PMIMR);
                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
                 I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask);
                 POSTING_READ(GEN6_PMIMR);
         }
-        spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
+        spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 
         return true;
 }
@@ -1077,14 +1077,14 @@ hsw_vebox_put_irq(struct intel_ring_buffer *ring)
         if (!dev->irq_enabled)
                 return;
 
-        spin_lock_irqsave(&dev_priv->rps.lock, flags);
+        spin_lock_irqsave(&dev_priv->irq_lock, flags);
         if (--ring->irq_refcount.pm == 0) {
                 u32 pm_imr = I915_READ(GEN6_PMIMR);
                 I915_WRITE_IMR(ring, ~0);
                 I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask);
                 POSTING_READ(GEN6_PMIMR);
         }
-        spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
+        spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 }
 
 static int