drm/i915: Broadwell expands ACTHD to 64bit

As Broadwell has an increased virtual address size, it requires more
than 32 bits to store offsets into its address space. This includes the
debug registers to track the current HEAD of the individual rings, which
may be anywhere within the per-process address spaces. In order to find
the full location, we need to read the high bits from a second register.
We then also need to expand our storage to keep track of the larger
address.

v2: Carefully read the two registers to catch wraparound between
    the reads.
v3: Use a WARN_ON rather than loop indefinitely on an unstable
    register read.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Timo Aaltonen <tjaalton@ubuntu.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Drop spurious hunk which conflicted.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 16 insertions, 6 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index bfb5d75cc1c5..0cba12948915 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -410,13 +410,20 @@ static void ring_write_tail(struct intel_ring_buffer *ring,
         I915_WRITE_TAIL(ring, value);
 }
 
-u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
+u64 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 {
         drm_i915_private_t *dev_priv = ring->dev->dev_private;
-        u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
-                        RING_ACTHD(ring->mmio_base) : ACTHD;
+        u64 acthd;
 
-        return I915_READ(acthd_reg);
+        if (INTEL_INFO(ring->dev)->gen >= 8)
+                acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
+                                         RING_ACTHD_UDW(ring->mmio_base));
+        else if (INTEL_INFO(ring->dev)->gen >= 4)
+                acthd = I915_READ(RING_ACTHD(ring->mmio_base));
+        else
+                acthd = I915_READ(ACTHD);
+
+        return acthd;
 }
 
 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
@@ -814,8 +821,11 @@ gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
         /* Workaround to force correct ordering between irq and seqno writes on
          * ivb (and maybe also on snb) by reading from a CS register (like
          * ACTHD) before reading the status page. */
-        if (!lazy_coherency)
-                intel_ring_get_active_head(ring);
+        if (!lazy_coherency) {
+                struct drm_i915_private *dev_priv = ring->dev->dev_private;
+                POSTING_READ(RING_ACTHD(ring->mmio_base));
+        }
+
         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 }