aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_ringbuffer.c
diff options
context:
space:
mode:
authorBen Widawsky <benjamin.widawsky@intel.com>2013-09-19 14:01:40 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-09-19 14:41:00 -0400
commit040d2baa6229d50c406340035766c4e99725bf3d (patch)
treeb89913b763b2fa552a737da48508381344931fba /drivers/gpu/drm/i915/intel_ringbuffer.c
parent3ccfd19dea7c5c85aa4b1f929a97a02b026ab356 (diff)
drm/i915: s/HAS_L3_GPU_CACHE/HAS_L3_DPF
We'd only ever used this define to denote whether or not we have the dynamic parity feature (DPF) and never to determine whether or not L3 exists. Baytrail is a good example of where L3 exists, and not DPF. This patch provides clarify in the code for future use cases which might want to actually query whether or not L3 exists. v2: Add /* DPF == dynamic parity feature */ Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 958b7d8fea8b..b67104aaade5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -569,7 +569,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
569 if (INTEL_INFO(dev)->gen >= 6) 569 if (INTEL_INFO(dev)->gen >= 6)
570 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); 570 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
571 571
572 if (HAS_L3_GPU_CACHE(dev)) 572 if (HAS_L3_DPF(dev))
573 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); 573 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
574 574
575 return ret; 575 return ret;
@@ -997,7 +997,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
997 997
998 spin_lock_irqsave(&dev_priv->irq_lock, flags); 998 spin_lock_irqsave(&dev_priv->irq_lock, flags);
999 if (ring->irq_refcount++ == 0) { 999 if (ring->irq_refcount++ == 0) {
1000 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) 1000 if (HAS_L3_DPF(dev) && ring->id == RCS)
1001 I915_WRITE_IMR(ring, 1001 I915_WRITE_IMR(ring,
1002 ~(ring->irq_enable_mask | 1002 ~(ring->irq_enable_mask |
1003 GT_PARITY_ERROR(dev))); 1003 GT_PARITY_ERROR(dev)));
@@ -1019,7 +1019,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
1019 1019
1020 spin_lock_irqsave(&dev_priv->irq_lock, flags); 1020 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1021 if (--ring->irq_refcount == 0) { 1021 if (--ring->irq_refcount == 0) {
1022 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) 1022 if (HAS_L3_DPF(dev) && ring->id == RCS)
1023 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); 1023 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1024 else 1024 else
1025 I915_WRITE_IMR(ring, ~0); 1025 I915_WRITE_IMR(ring, ~0);