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authorDaniel Vetter <daniel.vetter@ffwll.ch>2010-08-02 10:33:33 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-21 06:20:02 -0400
commit6c0e1c556ee659cd8c976cd175c0b70e209acb92 (patch)
tree23ed32b8fa8aec3bef7f9fae671e8f830e67846c /drivers/gpu/drm/i915/intel_ringbuffer.c
parent870e86ddc2d110124812b277643ed0f2767148ee (diff)
drm/i915: use new macros to access the ring start register
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 4b797e7dc95d..395c4d34b1e2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -157,7 +157,7 @@ static int init_ring_common(struct drm_device *dev,
157 ring->set_tail(dev, ring, 0); 157 ring->set_tail(dev, ring, 0);
158 158
159 /* Initialize the ring. */ 159 /* Initialize the ring. */
160 I915_WRITE(ring->regs.start, obj_priv->gtt_offset); 160 I915_WRITE_START(ring, obj_priv->gtt_offset);
161 head = ring->get_head(dev, ring); 161 head = ring->get_head(dev, ring);
162 162
163 /* G45 ring initialization fails to reset head to zero */ 163 /* G45 ring initialization fails to reset head to zero */
@@ -168,7 +168,7 @@ static int init_ring_common(struct drm_device *dev,
168 I915_READ(ring->regs.ctl), 168 I915_READ(ring->regs.ctl),
169 I915_READ(ring->regs.head), 169 I915_READ(ring->regs.head),
170 I915_READ_TAIL(ring), 170 I915_READ_TAIL(ring),
171 I915_READ(ring->regs.start)); 171 I915_READ_START(ring));
172 172
173 I915_WRITE(ring->regs.head, 0); 173 I915_WRITE(ring->regs.head, 0);
174 174
@@ -178,7 +178,7 @@ static int init_ring_common(struct drm_device *dev,
178 I915_READ(ring->regs.ctl), 178 I915_READ(ring->regs.ctl),
179 I915_READ(ring->regs.head), 179 I915_READ(ring->regs.head),
180 I915_READ_TAIL(ring), 180 I915_READ_TAIL(ring),
181 I915_READ(ring->regs.start)); 181 I915_READ_START(ring));
182 } 182 }
183 183
184 I915_WRITE(ring->regs.ctl, 184 I915_WRITE(ring->regs.ctl,
@@ -194,7 +194,7 @@ static int init_ring_common(struct drm_device *dev,
194 I915_READ(ring->regs.ctl), 194 I915_READ(ring->regs.ctl),
195 I915_READ(ring->regs.head), 195 I915_READ(ring->regs.head),
196 I915_READ_TAIL(ring), 196 I915_READ_TAIL(ring),
197 I915_READ(ring->regs.start)); 197 I915_READ_START(ring));
198 return -EIO; 198 return -EIO;
199 } 199 }
200 200
@@ -781,7 +781,6 @@ static const struct intel_ring_buffer render_ring = {
781 .regs = { 781 .regs = {
782 .ctl = PRB0_CTL, 782 .ctl = PRB0_CTL,
783 .head = PRB0_HEAD, 783 .head = PRB0_HEAD,
784 .start = PRB0_START
785 }, 784 },
786 .mmio_base = RENDER_RING_BASE, 785 .mmio_base = RENDER_RING_BASE,
787 .size = 32 * PAGE_SIZE, 786 .size = 32 * PAGE_SIZE,
@@ -818,7 +817,6 @@ static const struct intel_ring_buffer bsd_ring = {
818 .regs = { 817 .regs = {
819 .ctl = BSD_RING_CTL, 818 .ctl = BSD_RING_CTL,
820 .head = BSD_RING_HEAD, 819 .head = BSD_RING_HEAD,
821 .start = BSD_RING_START
822 }, 820 },
823 .mmio_base = BSD_RING_BASE, 821 .mmio_base = BSD_RING_BASE,
824 .size = 32 * PAGE_SIZE, 822 .size = 32 * PAGE_SIZE,
@@ -929,7 +927,6 @@ static const struct intel_ring_buffer gen6_bsd_ring = {
929 .regs = { 927 .regs = {
930 .ctl = GEN6_BSD_RING_CTL, 928 .ctl = GEN6_BSD_RING_CTL,
931 .head = GEN6_BSD_RING_HEAD, 929 .head = GEN6_BSD_RING_HEAD,
932 .start = GEN6_BSD_RING_START
933 }, 930 },
934 .mmio_base = GEN6_BSD_RING_BASE, 931 .mmio_base = GEN6_BSD_RING_BASE,
935 .size = 32 * PAGE_SIZE, 932 .size = 32 * PAGE_SIZE,