drm/i915: implement WADP0ClockGatingDisable

Found in Bspec vol4h South Display Engine Registers [CPT, PPT],
section "5.3.1  TRANS_CHICKEN_1—Transcoder Chicken Bits 1"

v2: Make it compile.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 6 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 596d97a68c68..fe8178bb7705 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3794,6 +3794,7 @@ static void ibx_init_clock_gating(struct drm_device *dev)
 static void cpt_init_clock_gating(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
+        int pipe;
 
         /*
          * On Ibex Peak and Cougar Point, we need to disable clock
@@ -3803,6 +3804,11 @@ static void cpt_init_clock_gating(struct drm_device *dev)
         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
                    DPLS_EDP_PPS_FIX_DIS);
+        /* WADP0ClockGatingDisable */
+        for_each_pipe(pipe) {
+                I915_WRITE(TRANS_CHICKEN1(pipe),
+                           TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
+        }
 }
 
 void intel_init_clock_gating(struct drm_device *dev)