Merge tag 'drm-intel-next-2013-02-01' of git://people.freedesktop.org/~danvet/drm-intel into drm-next

Daniel writes:
"Probably the last feature pull for 3.9, there's some fixes outstanding
thought that I'd like to sneak in. And maybe 3.8 takes a bit longer ...
Anyway, highlights of this pull:
- Kill the horrible IS_DISPLAYREG hack to handle the mmio offset movements
  on vlv, big thanks to Ville.
- Dynamic power well support for Haswell, shaves away a bit when only
  using the eDP port on pipe A (Paulo). Plus unclaimed register fixes
  uncovered by this.
- Clarifications of the gpu hang/reset state transitions, hopefully fixing
  a few spurious -EIO deaths in userspace.
- Haswell ELD fixes.
- Some more (pp)gtt cleanups from Ben.
- A few smaller things all over.

Plus all the stuff from the previous rather small pull request:
- Broadcast RBG improvements and reduced color range fixes from Ville.
- Ben is on a "kill legacy gtt code for good" spree, first pile of patches
  included.
- No-relocs and bo lut improvements for faster execbuf from Chris.
- Some refactorings from Imre."

* tag 'drm-intel-next-2013-02-01' of git://people.freedesktop.org/~danvet/drm-intel: (101 commits)
  GPU/i915: Fix acpi_bus_get_device() check in drivers/gpu/drm/i915/intel_opregion.c
  drm/i915: Set the SR01 "screen off" bit in i915_redisable_vga() too
  drm/i915: Kill IS_DISPLAYREG()
  drm/i915: Introduce i915_vgacntrl_reg()
  drm/i915: gen6_gmch_remove can be static
  drm/i915: dynamic Haswell display power well support
  drm/i915: check the power down well on assert_pipe()
  drm/i915: don't send DP "idle" pattern before "normal" on HSW PORT_A
  drm/i915: don't run hsw power well code on !hsw
  drm/i915: kill cargo-culted locking from power well code
  drm/i915: Only run idle processing from i915_gem_retire_requests_worker
  drm/i915: Fix CAGF for HSW
  drm/i915: Reclaim GTT space for failed PPGTT
  drm/i915: remove intel_gtt structure
  drm/i915: Add probe and remove to the gtt ops
  drm/i915: extract hw ppgtt setup/cleanup code
  drm/i915: pte_encode is gen6+
  drm/i915: vfuncs for ppgtt
  drm/i915: vfuncs for gtt_clear_range/insert_entries
  drm/i915: Error state should print /sys/kernel/debug
  ...

1 files changed, 44 insertions, 18 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ca9734529229..f7f67360e740 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3687,6 +3687,10 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
         reg |= GEN7_FF_VS_SCHED_HW;
         reg |= GEN7_FF_DS_SCHED_HW;
 
+        /* WaVSRefCountFullforceMissDisable */
+        if (IS_HASWELL(dev_priv->dev))
+                reg &= ~GEN7_FF_VS_REF_CNT_FFME;
+
         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
 }
 
@@ -4050,35 +4054,57 @@ void intel_init_clock_gating(struct drm_device *dev)
         dev_priv->display.init_clock_gating(dev);
 }
 
-/* Starting with Haswell, we have different power wells for
- * different parts of the GPU. This attempts to enable them all.
- */
-void intel_init_power_wells(struct drm_device *dev)
+void intel_set_power_well(struct drm_device *dev, bool enable)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
-        unsigned long power_wells[] = {
-                HSW_PWR_WELL_CTL1,
-                HSW_PWR_WELL_CTL2,
-                HSW_PWR_WELL_CTL4
-        };
-        int i;
+        bool is_enabled, enable_requested;
+        uint32_t tmp;
 
         if (!IS_HASWELL(dev))
                 return;
 
-        mutex_lock(&dev->struct_mutex);
+        tmp = I915_READ(HSW_PWR_WELL_DRIVER);
+        is_enabled = tmp & HSW_PWR_WELL_STATE;
+        enable_requested = tmp & HSW_PWR_WELL_ENABLE;
 
-        for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
-                int well = I915_READ(power_wells[i]);
+        if (enable) {
+                if (!enable_requested)
+                        I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
 
-                if ((well & HSW_PWR_WELL_STATE) == 0) {
-                        I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
-                        if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
-                                DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
+                if (!is_enabled) {
+                        DRM_DEBUG_KMS("Enabling power well\n");
+                        if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
+                                      HSW_PWR_WELL_STATE), 20))
+                                DRM_ERROR("Timeout enabling power well\n");
+                }
+        } else {
+                if (enable_requested) {
+                        I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
+                        DRM_DEBUG_KMS("Requesting to disable the power well\n");
                 }
         }
+}
 
-        mutex_unlock(&dev->struct_mutex);
+/*
+ * Starting with Haswell, we have a "Power Down Well" that can be turned off
+ * when not needed anymore. We have 4 registers that can request the power well
+ * to be enabled, and it will only be disabled if none of the registers is
+ * requesting it to be enabled.
+ */
+void intel_init_power_well(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        if (!IS_HASWELL(dev))
+                return;
+
+        /* For now, we need the power well to be always enabled. */
+        intel_set_power_well(dev, true);
+
+        /* We're taking over the BIOS, so clear any requests made by it since
+         * the driver is in charge now. */
+        if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
+                I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 }
 
 /* Set up chip specific power management-related functions */