drm/i915: add RPS configuration for Haswell

Most of the RPS and RC6 enabling functionality is similar to what we had
on Gen6/Gen7, so we preserve most of the registers.

Note that Haswell only has RC6, so account for that as well. As suggested
by Daniel Vetter, to reduce the amount of changes in the patch, we still
write the RC6p/RC6pp thresholds, but those are ignored on Haswell.

Note: Some discussion about the nature of the new tuning constants
popped up in review - the answer is that we don't know why they've
changed, but the guide from VPG with the magic numbers simply has
different values now.

v2: Squash fix for ?: vs | operation precende bug into this patch.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Added note to commit message. Squashed fix.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 25 insertions, 12 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ed9912ca1f82..4c6c26c5ad32 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2404,20 +2404,24 @@ static void gen6_enable_rps(struct drm_device *dev)
         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
 
+        /* Check if we are enabling RC6 */
         rc6_mode = intel_enable_rc6(dev_priv->dev);
         if (rc6_mode & INTEL_RC6_ENABLE)
                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
 
-        if (rc6_mode & INTEL_RC6p_ENABLE)
-                rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
+        /* We don't use those on Haswell */
+        if (!IS_HASWELL(dev)) {
+                if (rc6_mode & INTEL_RC6p_ENABLE)
+                        rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
 
-        if (rc6_mode & INTEL_RC6pp_ENABLE)
-                rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
+                if (rc6_mode & INTEL_RC6pp_ENABLE)
+                        rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
+        }
 
         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
-                        (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off",
-                        (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off",
-                        (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off");
+                        (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
+                        (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
+                        (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
 
         I915_WRITE(GEN6_RC_CONTROL,
                    rc6_mask |
@@ -2435,10 +2439,19 @@ static void gen6_enable_rps(struct drm_device *dev)
         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
                    dev_priv->max_delay << 24 |
                    dev_priv->min_delay << 16);
-        I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
-        I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
-        I915_WRITE(GEN6_RP_UP_EI, 100000);
-        I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
+
+        if (IS_HASWELL(dev)) {
+                I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+                I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+                I915_WRITE(GEN6_RP_UP_EI, 66000);
+                I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+        } else {
+                I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
+                I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
+                I915_WRITE(GEN6_RP_UP_EI, 100000);
+                I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
+        }
+
         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
         I915_WRITE(GEN6_RP_CONTROL,
                    GEN6_RP_MEDIA_TURBO |
@@ -2446,7 +2459,7 @@ static void gen6_enable_rps(struct drm_device *dev)
                    GEN6_RP_MEDIA_IS_GFX |
                    GEN6_RP_ENABLE |
                    GEN6_RP_UP_BUSY_AVG |
-                   GEN6_RP_DOWN_IDLE_CONT);
+                   (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
 
         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
                      500))