drm/i915: Refactor panel backlight controls

There were two instances of code to control the panel backlight and
neither handled the complete set of device variations.

Fixes:

  Bug 29716 - [GM965] Regression: Backlight resets to minimum when changing resolution
  https://bugs.freedesktop.org/show_bug.cgi?id=29716

And a bug on one of my PineView boxes which overflowed the backlight
value.

Incorporates part of a similar patch by Matthew Garrett that exposes a
native Intel backlight controller.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

1 files changed, 109 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index e7f5299d9d57..30abe7afc942 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -30,6 +30,8 @@
 
 #include "intel_drv.h"
 
+#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
+
 void
 intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
                        struct drm_display_mode *adjusted_mode)
@@ -109,3 +111,110 @@ done:
         dev_priv->pch_pf_pos = (x << 16) | y;
         dev_priv->pch_pf_size = (width << 16) | height;
 }
+
+static int is_backlight_combination_mode(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        if (IS_I965G(dev))
+                return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
+
+        if (IS_GEN2(dev))
+                return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
+
+        return 0;
+}
+
+u32 intel_panel_get_max_backlight(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 max;
+
+        if (HAS_PCH_SPLIT(dev)) {
+                max = I915_READ(BLC_PWM_PCH_CTL2) >> 16;
+        } else {
+                max = I915_READ(BLC_PWM_CTL);
+                if (IS_PINEVIEW(dev)) {
+                        max >>= 17;
+                } else {
+                        max >>= 16;
+                        if (!IS_I965G(dev))
+                                max &= ~1;
+                }
+
+                if (is_backlight_combination_mode(dev))
+                        max *= 0xff;
+        }
+
+        if (max == 0) {
+                /* XXX add code here to query mode clock or hardware clock
+                 * and program max PWM appropriately.
+                 */
+                DRM_ERROR("fixme: max PWM is zero.\n");
+                max = 1;
+        }
+
+        DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
+        return max;
+}
+
+u32 intel_panel_get_backlight(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 val;
+
+        if (HAS_PCH_SPLIT(dev)) {
+                val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
+        } else {
+                val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
+                if (IS_PINEVIEW(dev))
+                        val >>= 1;
+
+                if (is_backlight_combination_mode(dev)){
+                        u8 lbpc;
+
+                        val &= ~1;
+                        pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
+                        val *= lbpc;
+                        val >>= 1;
+                }
+        }
+
+        DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
+        return val;
+}
+
+static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
+        I915_WRITE(BLC_PWM_CPU_CTL, val | level);
+}
+
+void intel_panel_set_backlight(struct drm_device *dev, u32 level)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 tmp;
+
+        DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
+
+        if (HAS_PCH_SPLIT(dev))
+                return intel_pch_panel_set_backlight(dev, level);
+
+        if (is_backlight_combination_mode(dev)){
+                u32 max = intel_panel_get_max_backlight(dev);
+                u8 lpbc;
+
+                lpbc = level * 0xfe / max + 1;
+                level /= lpbc;
+                pci_write_config_byte(dev->pdev, PCI_LBPC, lpbc);
+        }
+
+        tmp = I915_READ(BLC_PWM_CTL);
+        if (IS_PINEVIEW(dev)) {
+                tmp &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
+                level <<= 1;
+        } else
+                tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
+        I915_WRITE(BLC_PWM_CTL, tmp | level);
+}