Merge remote branch 'anholt/drm-intel-next' into drm-next-stage

* anholt/drm-intel-next:
  drm/i915: Record batch buffer following GPU error
  drm/i915: give up on 8xx lid status
  drm/i915: reduce some of the duplication of tiling checking
  drm/i915: blow away userspace mappings before fence change
  drm/i915: move a gtt flush to the correct place
  agp/intel: official names for Pineview and Ironlake
  drm/i915: overlay: drop superflous gpu flushes
  drm/i915: overlay: nuke readback to flush wc caches
  drm/i915: provide self-refresh status in debugfs
  drm/i915: provide FBC status in debugfs
  drm/i915: fix drps disable so unload & re-load works
  drm/i915: Fix OGLC performance regression on 945
  drm/i915: Deobfuscate the render p-state obfuscation
  drm/i915: add dynamic performance control support for Ironlake
  drm/i915: enable memory self refresh on 9xx
  drm/i915: Don't reserve compatibility fence regs in KMS mode.
  drm/i915: Keep MCHBAR always enabled
  drm/i915: Replace open-coded eviction in i915_gem_idle()

1 files changed, 5 insertions, 20 deletions

diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 1b50d61c5aaa..c3fa406912b3 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -199,16 +199,11 @@ static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_over
 
 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay)
 {
-        struct drm_device *dev = overlay->dev;
-        drm_i915_private_t *dev_priv = dev->dev_private;
-
         if (OVERLAY_NONPHYSICAL(overlay->dev))
                 io_mapping_unmap_atomic(overlay->virt_addr);
 
         overlay->virt_addr = NULL;
 
-        I915_READ(OVADD); /* flush wc cashes */
-
         return;
 }
 
@@ -225,9 +220,7 @@ static int intel_overlay_on(struct intel_overlay *overlay)
         overlay->active = 1;
         overlay->hw_wedged = NEEDS_WAIT_FOR_FLIP;
 
-        BEGIN_LP_RING(6);
-        OUT_RING(MI_FLUSH);
-        OUT_RING(MI_NOOP);
+        BEGIN_LP_RING(4);
         OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
         OUT_RING(overlay->flip_addr | OFC_UPDATE);
         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
@@ -267,9 +260,7 @@ static void intel_overlay_continue(struct intel_overlay *overlay,
         if (tmp & (1 << 17))
                 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
 
-        BEGIN_LP_RING(4);
-        OUT_RING(MI_FLUSH);
-        OUT_RING(MI_NOOP);
+        BEGIN_LP_RING(2);
         OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
         OUT_RING(flip_addr);
         ADVANCE_LP_RING();
@@ -338,9 +329,7 @@ static int intel_overlay_off(struct intel_overlay *overlay)
         /* wait for overlay to go idle */
         overlay->hw_wedged = SWITCH_OFF_STAGE_1;
 
-        BEGIN_LP_RING(6);
-        OUT_RING(MI_FLUSH);
-        OUT_RING(MI_NOOP);
+        BEGIN_LP_RING(4);
         OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
         OUT_RING(flip_addr);
         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
@@ -358,9 +347,7 @@ static int intel_overlay_off(struct intel_overlay *overlay)
         /* turn overlay off */
         overlay->hw_wedged = SWITCH_OFF_STAGE_2;
 
-        BEGIN_LP_RING(6);
-        OUT_RING(MI_FLUSH);
-        OUT_RING(MI_NOOP);
+        BEGIN_LP_RING(4);
         OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
         OUT_RING(flip_addr);
         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
@@ -435,9 +422,7 @@ int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
 
                         overlay->hw_wedged = SWITCH_OFF_STAGE_2;
 
-                        BEGIN_LP_RING(6);
-                        OUT_RING(MI_FLUSH);
-                        OUT_RING(MI_NOOP);
+                        BEGIN_LP_RING(4);
                         OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
                         OUT_RING(flip_addr);
                         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);