drm/i915: use pipe_config for lvds dithering

Up to now we've relied on the bios to get this right for us. Let's try
out whether our code has improved a bit, since we should dither
always when the output bpp doesn't match the plane bpp.
- gen5+ should be fine, since we only use the bios hint as an upgrade.
- gen4 changes, since here dithering is still controlled in the lvds
  register.
- gen2/3 has implicit dithering depeding upon whether you use 2 or 3
  lvds pairs (which makes sense, since it only supports 8bpc pipe
  outpu configurations).
- hsw doesn't support lvds.

v2: Remove redudant dither setting.

v3: Completly drop reliance on dev_priv->lvds_dither.

v4: Enable dithering on gen2/3 only when we have a 18bpp panel, since
up-dithering to a 24bpp panel is not supported by the hw. Spotted by
Ville.

v5: Also only enable lvds port dithering on gen4 for 18bpp modes. In
practice this only excludes dithering a 10bpc plane down for a 24bpp
lvds panel. Not something we truly care about. Again noticed by Ville.

v6: Actually git add.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 10 insertions, 5 deletions

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 563f5052fcfc..84085454b104 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -136,7 +136,10 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
          * special lvds dither control bit on pch-split platforms, dithering is
          * only controlled through the PIPECONF reg. */
         if (INTEL_INFO(dev)->gen == 4) {
-                if (dev_priv->lvds_dither)
+                /* Bspec wording suggests that LVDS port dithering only exists
+                 * for 18bpp panels. */
+                if (intel_crtc->config.dither &&
+                    intel_crtc->config.pipe_bpp == 18)
                         temp |= LVDS_ENABLE_DITHER;
                 else
                         temp &= ~LVDS_ENABLE_DITHER;
@@ -335,7 +338,13 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
                 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
                               pipe_config->pipe_bpp, lvds_bpp);
                 pipe_config->pipe_bpp = lvds_bpp;
+
+                /* Make sure pre-965 set dither correctly for 18bpp panels. */
+                if (INTEL_INFO(dev)->gen < 4 && lvds_bpp == 18)
+                        pfit_control |= PANEL_8TO6_DITHER_ENABLE;
+
         }
+
         /*
          * We have timings from the BIOS for the panel, put them in
          * to the adjusted mode.  The CRTC will be set up for this mode,
@@ -470,10 +479,6 @@ out:
                 pfit_pgm_ratios = 0;
         }
 
-        /* Make sure pre-965 set dither correctly */
-        if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)
-                pfit_control |= PANEL_8TO6_DITHER_ENABLE;
-
         if (pfit_control != lvds_encoder->pfit_control ||
             pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) {
                 lvds_encoder->pfit_control = pfit_control;