drm/i915: More s/IS_IRONLAKE/HAS_PCH_SPLIT for Sandybridge.

I think this is pretty much correct.  Not really tested.

Signed-off-by: Eric Anholt <eric@anholt.net>

1 files changed, 12 insertions, 12 deletions

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index e91e81de5c71..222459ad178d 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -56,7 +56,7 @@ static void intel_lvds_set_backlight(struct drm_device *dev, int level)
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 blc_pwm_ctl, reg;
 
-        if (IS_IRONLAKE(dev))
+        if (HAS_PCH_SPLIT(dev))
                 reg = BLC_PWM_CPU_CTL;
         else
                 reg = BLC_PWM_CTL;
@@ -74,7 +74,7 @@ static u32 intel_lvds_get_max_backlight(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 reg;
 
-        if (IS_IRONLAKE(dev))
+        if (HAS_PCH_SPLIT(dev))
                 reg = BLC_PWM_PCH_CTL2;
         else
                 reg = BLC_PWM_CTL;
@@ -91,7 +91,7 @@ static void intel_lvds_set_power(struct drm_device *dev, bool on)
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 pp_status, ctl_reg, status_reg;
 
-        if (IS_IRONLAKE(dev)) {
+        if (HAS_PCH_SPLIT(dev)) {
                 ctl_reg = PCH_PP_CONTROL;
                 status_reg = PCH_PP_STATUS;
         } else {
@@ -137,7 +137,7 @@ static void intel_lvds_save(struct drm_connector *connector)
         u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg;
         u32 pwm_ctl_reg;
 
-        if (IS_IRONLAKE(dev)) {
+        if (HAS_PCH_SPLIT(dev)) {
                 pp_on_reg = PCH_PP_ON_DELAYS;
                 pp_off_reg = PCH_PP_OFF_DELAYS;
                 pp_ctl_reg = PCH_PP_CONTROL;
@@ -174,7 +174,7 @@ static void intel_lvds_restore(struct drm_connector *connector)
         u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg;
         u32 pwm_ctl_reg;
 
-        if (IS_IRONLAKE(dev)) {
+        if (HAS_PCH_SPLIT(dev)) {
                 pp_on_reg = PCH_PP_ON_DELAYS;
                 pp_off_reg = PCH_PP_OFF_DELAYS;
                 pp_ctl_reg = PCH_PP_CONTROL;
@@ -297,7 +297,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
         }
 
         /* full screen scale for now */
-        if (IS_IRONLAKE(dev))
+        if (HAS_PCH_SPLIT(dev))
                 goto out;
 
         /* 965+ wants fuzzy fitting */
@@ -327,7 +327,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
          * to register description and PRM.
          * Change the value here to see the borders for debugging
          */
-        if (!IS_IRONLAKE(dev)) {
+        if (!HAS_PCH_SPLIT(dev)) {
                 I915_WRITE(BCLRPAT_A, 0);
                 I915_WRITE(BCLRPAT_B, 0);
         }
@@ -548,7 +548,7 @@ static void intel_lvds_prepare(struct drm_encoder *encoder)
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 reg;
 
-        if (IS_IRONLAKE(dev))
+        if (HAS_PCH_SPLIT(dev))
                 reg = BLC_PWM_CPU_CTL;
         else
                 reg = BLC_PWM_CTL;
@@ -587,7 +587,7 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
          * settings.
          */
 
-        if (IS_IRONLAKE(dev))
+        if (HAS_PCH_SPLIT(dev))
                 return;
 
         /*
@@ -1027,7 +1027,7 @@ void intel_lvds_init(struct drm_device *dev)
                 return;
         }
 
-        if (IS_IRONLAKE(dev)) {
+        if (HAS_PCH_SPLIT(dev)) {
                 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
                         return;
                 if (dev_priv->edp_support) {
@@ -1130,7 +1130,7 @@ void intel_lvds_init(struct drm_device *dev)
          */
 
         /* Ironlake: FIXME if still fail, not try pipe mode now */
-        if (IS_IRONLAKE(dev))
+        if (HAS_PCH_SPLIT(dev))
                 goto failed;
 
         lvds = I915_READ(LVDS);
@@ -1151,7 +1151,7 @@ void intel_lvds_init(struct drm_device *dev)
                 goto failed;
 
 out:
-        if (IS_IRONLAKE(dev)) {
+        if (HAS_PCH_SPLIT(dev)) {
                 u32 pwm;
                 /* make sure PWM is enabled */
                 pwm = I915_READ(BLC_PWM_CPU_CTL2);