drm/i915/intel_i2c: use double-buffered writes

The GMBUS controller GMBUS3 register is double-buffered.  Take advantage
of this  by writing two 4-byte words before the first wait for HW_RDY.
This helps keep the GMBUS controller from becoming idle during long writes.

In fact, during experiments using the GMBUS interrupts, the HW_RDY
interrupt would only trigger for transactions >4 bytes after 2 writes
to GMBUS3.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 7 insertions, 7 deletions

diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 99a04f8bcb1f..f02e52aca746 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -262,13 +262,6 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
         POSTING_READ(GMBUS2 + reg_offset);
         while (len) {
-                if (wait_for(I915_READ(GMBUS2 + reg_offset) &
-                             (GMBUS_SATOER | GMBUS_HW_RDY),
-                             50))
-                        return -ETIMEDOUT;
-                if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
-                        return -ENXIO;
-
                 val = loop = 0;
                 do {
                         val |= *buf++ << (8 * loop);
@@ -276,6 +269,13 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 
                 I915_WRITE(GMBUS3 + reg_offset, val);
                 POSTING_READ(GMBUS2 + reg_offset);
+
+                if (wait_for(I915_READ(GMBUS2 + reg_offset) &
+                             (GMBUS_SATOER | GMBUS_HW_RDY),
+                             50))
+                        return -ETIMEDOUT;
+                if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
+                        return -ENXIO;
         }
         return 0;
 }