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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2012-05-04 16:18:21 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-05-08 08:15:51 -0400
commitecb978515c88183b111b8994acd6b572b1361a72 (patch)
treee822de5e92160d578f8bb58df830f77a7730218f /drivers/gpu/drm/i915/intel_hdmi.c
parentfa193ff7999a7c1cdd1723f1cbc4a108540ca478 (diff)
drm/i915: disable the infoframe before changing it
That's what the VIDEO_DIP_CTL documentation says we need to do. Except when it's the AVI InfoFrame and we're ironlake_write_infoframe. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_hdmi.c')
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 661fed48c5b9..6c96bb54e967 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -153,6 +153,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder,
153 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 153 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
154 val |= intel_infoframe_index(frame); 154 val |= intel_infoframe_index(frame);
155 155
156 val &= ~intel_infoframe_enable(frame);
156 val |= VIDEO_DIP_ENABLE; 157 val |= VIDEO_DIP_ENABLE;
157 158
158 I915_WRITE(VIDEO_DIP_CTL, val); 159 I915_WRITE(VIDEO_DIP_CTL, val);
@@ -185,6 +186,13 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder,
185 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 186 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
186 val |= intel_infoframe_index(frame); 187 val |= intel_infoframe_index(frame);
187 188
189 /* The DIP control register spec says that we need to update the AVI
190 * infoframe without clearing its enable bit */
191 if (frame->type == DIP_TYPE_AVI)
192 val |= VIDEO_DIP_ENABLE_AVI;
193 else
194 val &= ~intel_infoframe_enable(frame);
195
188 val |= VIDEO_DIP_ENABLE; 196 val |= VIDEO_DIP_ENABLE;
189 197
190 I915_WRITE(reg, val); 198 I915_WRITE(reg, val);
@@ -217,6 +225,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
217 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 225 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
218 val |= intel_infoframe_index(frame); 226 val |= intel_infoframe_index(frame);
219 227
228 val &= ~intel_infoframe_enable(frame);
220 val |= VIDEO_DIP_ENABLE; 229 val |= VIDEO_DIP_ENABLE;
221 230
222 I915_WRITE(reg, val); 231 I915_WRITE(reg, val);