Merge tag 'drm-intel-next-2014-11-21-fixed' of git://anongit.freedesktop.org/drm-intel into drm-next

drm-intel-next-2014-11-21:
- infoframe tracking (for fastboot) from Jesse
- start of the dri1/ums support removal
- vlv forcewake timeout fixes (Imre)
- bunch of patches to polish the rps code (Imre) and improve it on bdw (Tom
  O'Rourke)
- on-demand pinning for execlist contexts
- vlv/chv backlight improvements (Ville)
- gen8+ render ctx w/a work from various people
- skl edp programming (Satheeshakrishna et al.)
- psr docbook (Rodrigo)
- piles of little fixes and improvements all over, as usual

* tag 'drm-intel-next-2014-11-21-fixed' of git://anongit.freedesktop.org/drm-intel: (117 commits)
  drm/i915: Don't pin LRC in GGTT when dumping in debugfs
  drm/i915: Update DRIVER_DATE to 20141121
  drm/i915/g4x: fix g4x infoframe readout
  drm/i915: Only call mod_timer() if not already pending
  drm/i915: Don't rely upon encoder->type for infoframe hw state readout
  drm/i915: remove the IRQs enabled WARN from intel_disable_gt_powersave
  drm/i915: Use ggtt error obj capture helper for gen8 semaphores
  drm/i915: vlv: increase timeout when setting idle GPU freq
  drm/i915: vlv: fix cdclk setting during modeset while suspended
  drm/i915: Dump hdmi pipe_config state
  drm/i915: Gen9 shadowed registers
  drm/i915/skl: Gen9 multi-engine forcewake
  drm/i915: Read power well status before other registers for drpc info
  drm/i915: Pin tiled objects for L-shaped configs
  drm/i915: Update ring freq for full gpu freq range
  drm/i915: change initial rps frequency for gen8
  drm/i915: Keep min freq above floor on HSW/BDW
  drm/i915: Use efficient frequency for HSW/BDW
  drm/i915: Can i915_gem_init_ioctl
  drm/i915: Sanitize ->lastclose
  ...

1 files changed, 69 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 29baa53aef90..ec873338e84d 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -166,6 +166,19 @@ static void g4x_write_infoframe(struct drm_encoder *encoder,
         POSTING_READ(VIDEO_DIP_CTL);
 }
 
+static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+        u32 val = I915_READ(VIDEO_DIP_CTL);
+
+        if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK))
+                return val & VIDEO_DIP_ENABLE;
+
+        return false;
+}
+
 static void ibx_write_infoframe(struct drm_encoder *encoder,
                                 enum hdmi_infoframe_type type,
                                 const void *frame, ssize_t len)
@@ -204,6 +217,17 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,
         POSTING_READ(reg);
 }
 
+static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+        int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+        u32 val = I915_READ(reg);
+
+        return val & VIDEO_DIP_ENABLE;
+}
+
 static void cpt_write_infoframe(struct drm_encoder *encoder,
                                 enum hdmi_infoframe_type type,
                                 const void *frame, ssize_t len)
@@ -245,6 +269,17 @@ static void cpt_write_infoframe(struct drm_encoder *encoder,
         POSTING_READ(reg);
 }
 
+static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+        int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
+        u32 val = I915_READ(reg);
+
+        return val & VIDEO_DIP_ENABLE;
+}
+
 static void vlv_write_infoframe(struct drm_encoder *encoder,
                                 enum hdmi_infoframe_type type,
                                 const void *frame, ssize_t len)
@@ -283,6 +318,17 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
         POSTING_READ(reg);
 }
 
+static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+        int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
+        u32 val = I915_READ(reg);
+
+        return val & VIDEO_DIP_ENABLE;
+}
+
 static void hsw_write_infoframe(struct drm_encoder *encoder,
                                 enum hdmi_infoframe_type type,
                                 const void *frame, ssize_t len)
@@ -320,6 +366,18 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
         POSTING_READ(ctl_reg);
 }
 
+static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
+        u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
+        u32 val = I915_READ(ctl_reg);
+
+        return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+                      VIDEO_DIP_ENABLE_VS_HSW);
+}
+
 /*
  * The data we write to the DIP data buffer registers is 1 byte bigger than the
  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
@@ -724,6 +782,9 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
         if (tmp & HDMI_MODE_SELECT_HDMI)
                 pipe_config->has_hdmi_sink = true;
 
+        if (intel_hdmi->infoframe_enabled(&encoder->base))
+                pipe_config->has_infoframe = true;
+
         if (tmp & SDVO_AUDIO_ENABLE)
                 pipe_config->has_audio = true;
 
@@ -925,6 +986,9 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 
         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
 
+        if (pipe_config->has_hdmi_sink)
+                pipe_config->has_infoframe = true;
+
         if (intel_hdmi->color_range_auto) {
                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
                 if (pipe_config->has_hdmi_sink &&
@@ -1619,18 +1683,23 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
         if (IS_VALLEYVIEW(dev)) {
                 intel_hdmi->write_infoframe = vlv_write_infoframe;
                 intel_hdmi->set_infoframes = vlv_set_infoframes;
+                intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
         } else if (IS_G4X(dev)) {
                 intel_hdmi->write_infoframe = g4x_write_infoframe;
                 intel_hdmi->set_infoframes = g4x_set_infoframes;
+                intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
         } else if (HAS_DDI(dev)) {
                 intel_hdmi->write_infoframe = hsw_write_infoframe;
                 intel_hdmi->set_infoframes = hsw_set_infoframes;
+                intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
         } else if (HAS_PCH_IBX(dev)) {
                 intel_hdmi->write_infoframe = ibx_write_infoframe;
                 intel_hdmi->set_infoframes = ibx_set_infoframes;
+                intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
         } else {
                 intel_hdmi->write_infoframe = cpt_write_infoframe;
                 intel_hdmi->set_infoframes = cpt_set_infoframes;
+                intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
         }
 
         if (HAS_DDI(dev))