drm/i915: start writing infoframes at address 0 on gen 4

Make sure we're doing the right thing, just like we do on gen5+.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index b84d19d0eaed..af88313d72d0 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -132,7 +132,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder,
         else
                 return;
 
-        val &= ~VIDEO_DIP_SELECT_MASK;
+        val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
         val |= intel_infoframe_index(frame);
 
         val |= VIDEO_DIP_ENABLE;