drm/i915: More s/IS_IRONLAKE/HAS_PCH_SPLIT for Sandybridge.

I think this is pretty much correct.  Not really tested.

Signed-off-by: Eric Anholt <eric@anholt.net>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 0e268deed761..a30f8bfc1985 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -82,7 +82,7 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
          * we do this anyway which shows more stable in testing.
          */
-        if (IS_IRONLAKE(dev)) {
+        if (HAS_PCH_SPLIT(dev)) {
                 I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE);
                 POSTING_READ(hdmi_priv->sdvox_reg);
         }
@@ -99,7 +99,7 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
         /* HW workaround, need to write this twice for issue that may result
          * in first write getting masked.
          */
-        if (IS_IRONLAKE(dev)) {
+        if (HAS_PCH_SPLIT(dev)) {
                 I915_WRITE(hdmi_priv->sdvox_reg, temp);
                 POSTING_READ(hdmi_priv->sdvox_reg);
         }