diff options
author | Vandana Kannan <vandana.kannan@intel.com> | 2014-08-05 10:51:22 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-08-08 11:43:24 -0400 |
commit | f769cd247d2be5af377adf82882eddd1dce183c4 (patch) | |
tree | 283fce94ff58babcb01ec26e196441feaf58504c /drivers/gpu/drm/i915/intel_drv.h | |
parent | be71eabebaf9f142612d34d42292b454e984dcb5 (diff) |
drm/i915: Set M2_N2 registers during mode set
For Gen < 8, set M2_N2 registers on every mode set. This is required to make
sure M2_N2 registers are set during boot, resume from sleep for cross-
checking the state. The register is set only if DRRS is supported.
v2: Patch rebased
v3: Daniel's review comments
- Removed HAS_DRRS(dev) and added bool has_drrs to pipe_config to
track drrs support
v4: Jesse's review comments
- Made changes to set m2_n2 in intel_dp_set_m_n()
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_drv.h')
-rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 4b2664bd5b81..7a3cac095afe 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h | |||
@@ -324,6 +324,7 @@ struct intel_crtc_config { | |||
324 | 324 | ||
325 | /* m2_n2 for eDP downclock */ | 325 | /* m2_n2 for eDP downclock */ |
326 | struct intel_link_m_n dp_m2_n2; | 326 | struct intel_link_m_n dp_m2_n2; |
327 | bool has_drrs; | ||
327 | 328 | ||
328 | /* | 329 | /* |
329 | * Frequence the dpll for the port should run at. Differs from the | 330 | * Frequence the dpll for the port should run at. Differs from the |
@@ -877,6 +878,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv); | |||
877 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); | 878 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); |
878 | void intel_dp_get_m_n(struct intel_crtc *crtc, | 879 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
879 | struct intel_crtc_config *pipe_config); | 880 | struct intel_crtc_config *pipe_config); |
881 | void intel_dp_set_m_n(struct intel_crtc *crtc); | ||
880 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); | 882 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
881 | void | 883 | void |
882 | ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, | 884 | ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
@@ -892,7 +894,6 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode, | |||
892 | int intel_format_to_fourcc(int format); | 894 | int intel_format_to_fourcc(int format); |
893 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); | 895 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); |
894 | 896 | ||
895 | |||
896 | /* intel_dp.c */ | 897 | /* intel_dp.c */ |
897 | void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); | 898 | void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); |
898 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, | 899 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |