drm/i915: Add intel_pipe_wm and prepare for watermark pre-compute

Introduce a new struct intel_pipe_wm which contains all the
watermarks for a single pipe. Use it to unify the LP0 and LP1+
watermark computations so that we can just iterate through the
watermark levels neatly and call ilk_compute_wm_level() for each.

Also add another tool ilk_wm_merge() that merges the LP1+ watermarks
from all pipes. For that, embed one intel_pipe_wm inside intel_crtc that
contains the currently valid watermarks for each pipe.

This is mainly preparatory work for pre-computing the watermarks for
each pipe and merging them at a later time. For now the merging still
happens immediately.

v2: Add some comments about level 0 DDB split and intel_wm_config
    Add WARN_ON for level 0 being disabled
    s/lp_wm/merged

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 12 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 189257df7a0f..5d5d34911a7e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -309,6 +309,12 @@ struct intel_crtc_config {
         bool double_wide;
 };
 
+struct intel_pipe_wm {
+        struct intel_wm_level wm[5];
+        uint32_t linetime;
+        bool fbc_wm_enabled;
+};
+
 struct intel_crtc {
         struct drm_crtc base;
         enum pipe pipe;
@@ -349,6 +355,12 @@ struct intel_crtc {
         /* Access to these should be protected by dev_priv->irq_lock. */
         bool cpu_fifo_underrun_disabled;
         bool pch_fifo_underrun_disabled;
+
+        /* per-pipe watermark state */
+        struct {
+                /* watermarks currently being used  */
+                struct intel_pipe_wm active;
+        } wm;
 };
 
 struct intel_plane_wm_parameters {