drm/i915: store adjusted dotclock in adjusted_mode->clock

... not the port clock. This allows us to kill the funny semantics
around pixel_target_clock.

Since the dpll code still needs the real port clock, add a new
port_clock field to the pipe configuration. Handling the default case
for that one is a bit tricky, since encoders might not consistently
overwrite it when retrying the crtc/encoder bw arbitrage step in the
compute config stage. Hence we need to always clear port_clock and
update it again if the encoder hasn't put in something more specific.
This can't be done in one step since the encoder might want to adjust
the mode first.

I was a bit on the fence whether I should subsume the pixel multiplier
handling into the port_clock, too. But then I decided against this
since it's on an abstract level still the dotclock of the adjusted
mode, and only our hw makes it a bit special due to the separate pixel
mulitplier setting (which requires that the dpll runs at the
non-multiplied dotclock).

So after this patch the adjusted_mode accurately describes the mode we
feed into the port, after the panel fitter and pixel multiplier (or
line doubling, if we ever bother with that) have done their job.
Since the fdi link is between the pfit and the pixel multiplier steps
we need to be careful with calculating the fdi link config.

v2: Fix up ilk cpu pll handling.

v3: Introduce an fdi_dotclock variable in ironlake_fdi_compute_config
to make it clearer that we transmit the adjusted_mode without the
pixel multiplier taken into account. The old code multiplied the the
available link bw with the pixel multiplier, which results in the same
fdi configuration, but is much more confusing.

v4: Rebase on top of Imre's is_cpu_edp removal.

v5: Rebase on top of Paulo's haswell watermark fixes, which introduce
a new place which looked at the pixel_clock and so needed conversion.

v6: Split out prep patches as requested by Paulo Zanoni. Also rebase
on top of the fdi dotclock handling fix in the fdi lanes/bw
computation code.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v3)
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 7 insertions, 11 deletions

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3b490c097400..759a1c5d170d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -677,7 +677,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
         int bpp, mode_rate;
         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
-        int target_clock, link_avail, link_clock;
+        int link_avail, link_clock;
 
         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
                 pipe_config->has_pch_encoder = true;
@@ -694,8 +694,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
                         intel_pch_panel_fitting(intel_crtc, pipe_config,
                                                 intel_connector->panel.fitting_mode);
         }
-        /* We need to take the panel's fixed mode into account. */
-        target_clock = adjusted_mode->clock;
 
         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
                 return false;
@@ -711,7 +709,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
                 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
 
         for (; bpp >= 6*3; bpp -= 2*3) {
-                mode_rate = intel_dp_link_required(target_clock, bpp);
+                mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
 
                 for (clock = 0; clock <= max_clock; clock++) {
                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
@@ -746,18 +744,17 @@ found:
 
         intel_dp->link_bw = bws[clock];
         intel_dp->lane_count = lane_count;
-        adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
         pipe_config->pipe_bpp = bpp;
-        pipe_config->pixel_target_clock = target_clock;
+        pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 
         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
                       intel_dp->link_bw, intel_dp->lane_count,
-                      adjusted_mode->clock, bpp);
+                      pipe_config->port_clock, bpp);
         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
                       mode_rate, link_avail);
 
         intel_link_compute_m_n(bpp, lane_count,
-                               target_clock, adjusted_mode->clock,
+                               adjusted_mode->clock, pipe_config->port_clock,
                                &pipe_config->dp_m_n);
 
         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
@@ -788,12 +785,11 @@ static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 dpa_ctl;
 
-        DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
-                      crtc->config.adjusted_mode.clock);
+        DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
         dpa_ctl = I915_READ(DP_A);
         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 
-        if (crtc->config.adjusted_mode.clock == 162000) {
+        if (crtc->config.port_clock == 162000) {
                 /* For a long time we've carried around a ILK-DevA w/a for the
                  * 160MHz clock. If we're really unlucky, it's still required.
                  */