drm/i915: Add additional pipe parameter for vlv_dpio_read and vlv_dpio_write. v2

The patch doesn't contain functional change, but is to prepare for
future platform which has different DPIO phy.  The additional pipe
parameter will use to select which phy to target for.

v2: Update the commit message and add static for the new function.
(Jani/Ville)

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 22 insertions, 16 deletions

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c192dbb8a36c..d6eba380ee2e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1746,16 +1746,16 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
 
         mutex_lock(&dev_priv->dpio_lock);
 
-        val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
+        val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
         val = 0;
         if (pipe)
                 val |= (1<<21);
         else
                 val &= ~(1<<21);
         val |= 0x001000c4;
-        vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
-        vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
-        vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
+        vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
 
         mutex_unlock(&dev_priv->dpio_lock);
 
@@ -1769,26 +1769,29 @@ static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
         struct drm_device *dev = encoder->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_crtc *intel_crtc =
+                to_intel_crtc(encoder->base.crtc);
         int port = vlv_dport_to_channel(dport);
+        int pipe = intel_crtc->pipe;
 
         if (!IS_VALLEYVIEW(dev))
                 return;
 
         /* Program Tx lane resets to default */
         mutex_lock(&dev_priv->dpio_lock);
-        vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
                          DPIO_PCS_TX_LANE2_RESET |
                          DPIO_PCS_TX_LANE1_RESET);
-        vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
                                  DPIO_PCS_CLK_SOFT_RESET);
 
         /* Fix up inter-pair skew failure */
-        vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
-        vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
-        vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
         mutex_unlock(&dev_priv->dpio_lock);
 }
 
@@ -1923,10 +1926,13 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
+        struct intel_crtc *intel_crtc =
+                to_intel_crtc(dport->base.base.crtc);
         unsigned long demph_reg_value, preemph_reg_value,
                 uniqtranscale_reg_value;
         uint8_t train_set = intel_dp->train_set[0];
         int port = vlv_dport_to_channel(dport);
+        int pipe = intel_crtc->pipe;
 
         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
         case DP_TRAIN_PRE_EMPHASIS_0:
@@ -2002,14 +2008,14 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
         }
 
         mutex_lock(&dev_priv->dpio_lock);
-        vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
-        vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
-        vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
                          uniqtranscale_reg_value);
-        vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
-        vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
-        vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
-        vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
+        vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
+        vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
         mutex_unlock(&dev_priv->dpio_lock);
 
         return 0;