drm/i915/dp: correct eDP lane count and bpp

With the old check we'd never set lane_count or bpp to different values
on PCH attached eDP panels.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

1 files changed, 4 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1b736637e13e..714e553960fd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -672,8 +672,10 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
                 intel_dp = enc_to_intel_dp(encoder);
                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
                         lane_count = intel_dp->lane_count;
-                        if (is_pch_edp(intel_dp))
-                                bpp = dev_priv->edp.bpp;
+                        break;
+                } else if (is_edp(intel_dp)) {
+                        lane_count = dev_priv->edp.lanes;
+                        bpp = dev_priv->edp.bpp;
                         break;
                 }
         }