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authorKeith Packard <keithp@keithp.com>2009-06-12 01:30:32 -0400
committerKeith Packard <keithp@keithp.com>2009-06-18 18:54:12 -0400
commita5b3da543d4882d57a2f3e05d37ad8e1e1453489 (patch)
treed2e5be7d8209fdf033338de6d4837442250c161d /drivers/gpu/drm/i915/intel_dp.c
parentb11248df4c0decb1e473d5025f237be32c0f67bb (diff)
drm/i915: Clarify error returns from display port aux channel I/O
Use distinct error return values for each kind of aux channel I/O failure. Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c20
1 files changed, 13 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3f8d7b449e70..818fe34f2b5c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -209,15 +209,19 @@ intel_dp_aux_ch(struct intel_output *intel_output,
209 209
210 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 210 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
211 printk(KERN_ERR "dp_aux_ch not done status 0x%08x\n", status); 211 printk(KERN_ERR "dp_aux_ch not done status 0x%08x\n", status);
212 return -1; 212 return -EBUSY;
213 } 213 }
214 214
215 /* Check for timeout or receive error. 215 /* Check for timeout or receive error.
216 * Timeouts occur when the sink is not connected 216 * Timeouts occur when the sink is not connected
217 */ 217 */
218 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_RECEIVE_ERROR)) { 218 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
219 printk(KERN_ERR "dp_aux_ch error status 0x%08x\n", status); 219 printk(KERN_ERR "dp_aux_ch receive error status 0x%08x\n", status);
220 return -1; 220 return -EIO;
221 }
222 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
223 printk(KERN_ERR "dp_aux_ch timeout status 0x%08x\n", status);
224 return -ETIMEDOUT;
221 } 225 }
222 226
223 /* Unload any bytes sent back from the other side */ 227 /* Unload any bytes sent back from the other side */
@@ -263,7 +267,7 @@ intel_dp_aux_native_write(struct intel_output *intel_output,
263 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 267 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
264 udelay(100); 268 udelay(100);
265 else 269 else
266 return -1; 270 return -EIO;
267 } 271 }
268 return send_bytes; 272 return send_bytes;
269} 273}
@@ -299,7 +303,9 @@ intel_dp_aux_native_read(struct intel_output *intel_output,
299 for (;;) { 303 for (;;) {
300 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, 304 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes,
301 reply, reply_bytes); 305 reply, reply_bytes);
302 if (ret <= 0) 306 if (ret == 0)
307 return -EPROTO;
308 if (ret < 0)
303 return ret; 309 return ret;
304 ack = reply[0]; 310 ack = reply[0];
305 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { 311 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
@@ -309,7 +315,7 @@ intel_dp_aux_native_read(struct intel_output *intel_output,
309 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 315 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
310 udelay(100); 316 udelay(100);
311 else 317 else
312 return -1; 318 return -EIO;
313 } 319 }
314} 320}
315 321