drm/i915: Enable aspect/centering panel fitting for Ironlake.

v2: Hook in DP paths to keep FULLSCREEN panel fitting on eDP.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>

1 files changed, 5 insertions, 15 deletions

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c4c5868a8aa0..cee5d9ceb3b8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -523,21 +523,9 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 
         if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
             dev_priv->panel_fixed_mode) {
-                struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode;
-
-                adjusted_mode->hdisplay = fixed_mode->hdisplay;
-                adjusted_mode->hsync_start = fixed_mode->hsync_start;
-                adjusted_mode->hsync_end = fixed_mode->hsync_end;
-                adjusted_mode->htotal = fixed_mode->htotal;
-
-                adjusted_mode->vdisplay = fixed_mode->vdisplay;
-                adjusted_mode->vsync_start = fixed_mode->vsync_start;
-                adjusted_mode->vsync_end = fixed_mode->vsync_end;
-                adjusted_mode->vtotal = fixed_mode->vtotal;
-
-                adjusted_mode->clock = fixed_mode->clock;
-                drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
-
+                intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
+                intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
+                                        mode, adjusted_mode);
                 /*
                  * the mode->clock is used to calculate the Data&Link M/N
                  * of the pipe. For the eDP the fixed clock should be used.
@@ -572,8 +560,10 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
                               "count %d clock %d\n",
                               intel_dp->link_bw, intel_dp->lane_count,
                               adjusted_mode->clock);
+
                 return true;
         }
+
         return false;
 }