diff options
author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2010-12-20 14:34:20 -0500 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2011-01-11 15:35:40 -0500 |
commit | a6044e23b784544fe567db75dbf9c4f684bd6d5b (patch) | |
tree | e2828ee5e59ba7e073283d5c890352892f22f793 /drivers/gpu/drm/i915/intel_display.c | |
parent | bee17e5ae6b68d21b9d193f34ccefeef9d4fffe0 (diff) |
drm/i915: support overclocking on Sandy Bridge
In some configuration, the PCU may allow us to overclock the GPU.
Check for this case and adjust the max frequency as appropriate. Also
initialize the min/max frequencies to default values as indicated by
hardware.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index bc829bbc14c8..efa88551cbe4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -6147,6 +6147,10 @@ void intel_init_emon(struct drm_device *dev) | |||
6147 | 6147 | ||
6148 | void gen6_enable_rps(struct drm_i915_private *dev_priv) | 6148 | void gen6_enable_rps(struct drm_i915_private *dev_priv) |
6149 | { | 6149 | { |
6150 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | ||
6151 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | ||
6152 | u32 pcu_mbox; | ||
6153 | int cur_freq, min_freq, max_freq; | ||
6150 | int i; | 6154 | int i; |
6151 | 6155 | ||
6152 | /* Here begins a magic sequence of register writes to enable | 6156 | /* Here begins a magic sequence of register writes to enable |
@@ -6218,6 +6222,29 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) | |||
6218 | 500)) | 6222 | 500)) |
6219 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | 6223 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); |
6220 | 6224 | ||
6225 | min_freq = (rp_state_cap & 0xff0000) >> 16; | ||
6226 | max_freq = rp_state_cap & 0xff; | ||
6227 | cur_freq = (gt_perf_status & 0xff00) >> 8; | ||
6228 | |||
6229 | /* Check for overclock support */ | ||
6230 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | ||
6231 | 500)) | ||
6232 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | ||
6233 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS); | ||
6234 | pcu_mbox = I915_READ(GEN6_PCODE_DATA); | ||
6235 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | ||
6236 | 500)) | ||
6237 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | ||
6238 | if (pcu_mbox & (1<<31)) { /* OC supported */ | ||
6239 | max_freq = pcu_mbox & 0xff; | ||
6240 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100); | ||
6241 | } | ||
6242 | |||
6243 | /* In units of 100MHz */ | ||
6244 | dev_priv->max_delay = max_freq; | ||
6245 | dev_priv->min_delay = min_freq; | ||
6246 | dev_priv->cur_delay = cur_freq; | ||
6247 | |||
6221 | /* requires MSI enabled */ | 6248 | /* requires MSI enabled */ |
6222 | I915_WRITE(GEN6_PMIER, | 6249 | I915_WRITE(GEN6_PMIER, |
6223 | GEN6_PM_MBOX_EVENT | | 6250 | GEN6_PM_MBOX_EVENT | |