drm/i915: fix tiling on IGDNG

It seems that on IGDNG the same swizzling setup always applys.
And front buffer tiling needs to set address swizzle in display
arb control too.

Fix plane tricle feed setting in v1 which should be disable bit,
and always setup address swizzle to let hardware care for buffer
tiling in all cases.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>

1 files changed, 10 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 867a969980ec..d7c7fa489872 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1064,6 +1064,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                         dspcntr &= ~DISPPLANE_TILED;
         }
 
+        if (IS_IGDNG(dev))
+                /* must disable */
+                dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
+
         I915_WRITE(dspcntr_reg, dspcntr);
 
         Start = obj_priv->gtt_offset;
@@ -2719,6 +2723,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 
         intel_wait_for_vblank(dev);
 
+        if (IS_IGDNG(dev)) {
+                /* enable address swizzle for tiling buffer */
+                temp = I915_READ(DISP_ARB_CTL);
+                I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
+        }
+
         I915_WRITE(dspcntr_reg, dspcntr);
 
         /* Flush the plane changes */