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authorZhenyu Wang <zhenyu.z.wang@intel.com>2009-03-24 02:02:43 -0400
committerEric Anholt <eric@anholt.net>2009-04-01 18:22:05 -0400
commit7026d4ac1fc134566c2c946e6c0d849fc03ba7b7 (patch)
tree3845375aa46b8552e6857d5c64982fabd423ef14 /drivers/gpu/drm/i915/intel_display.c
parente642c6f1d2ebea41b8d7ccc132734b74b5821034 (diff)
drm/i915: Fix SDVO TV support
This brings SDVO TV support from 2D driver, including origin fix f1ca56e17d0 and later fix 2fcf4fcccfe. Also fix wrong modeline definitions for SDVO TV. Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0b33760b04cb..64773ce52964 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1106,6 +1106,26 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1106 return -EINVAL; 1106 return -EINVAL;
1107 } 1107 }
1108 1108
1109 /* SDVO TV has fixed PLL values depend on its clock range,
1110 this mirrors vbios setting. */
1111 if (is_sdvo && is_tv) {
1112 if (adjusted_mode->clock >= 100000
1113 && adjusted_mode->clock < 140500) {
1114 clock.p1 = 2;
1115 clock.p2 = 10;
1116 clock.n = 3;
1117 clock.m1 = 16;
1118 clock.m2 = 8;
1119 } else if (adjusted_mode->clock >= 140500
1120 && adjusted_mode->clock <= 200000) {
1121 clock.p1 = 1;
1122 clock.p2 = 10;
1123 clock.n = 6;
1124 clock.m1 = 12;
1125 clock.m2 = 8;
1126 }
1127 }
1128
1109 if (IS_IGD(dev)) 1129 if (IS_IGD(dev))
1110 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; 1130 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
1111 else 1131 else