drm/i915: Set M2_N2 registers during mode set

For Gen < 8, set M2_N2 registers on every mode set. This is required to make
sure M2_N2 registers are set during boot, resume from sleep for cross-
checking the state. The register is set only if DRRS is supported.

v2: Patch rebased

v3: Daniel's review comments
	- Removed HAS_DRRS(dev) and added bool has_drrs to pipe_config to
	track drrs support

v4: Jesse's review comments
	- Made changes to set m2_n2 in intel_dp_set_m_n()

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 21 insertions, 7 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 018fb7222f60..acee1416eb93 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -91,11 +91,11 @@ static int intel_framebuffer_init(struct drm_device *dev,
                                   struct intel_framebuffer *ifb,
                                   struct drm_mode_fb_cmd2 *mode_cmd,
                                   struct drm_i915_gem_object *obj);
-static void intel_dp_set_m_n(struct intel_crtc *crtc);
 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
-                                         struct intel_link_m_n *m_n);
+                                         struct intel_link_m_n *m_n,
+                                         struct intel_link_m_n *m2_n2);
 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 static void intel_set_pipe_csc(struct drm_crtc *crtc);
@@ -3980,7 +3980,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 
         if (intel_crtc->config.has_pch_encoder) {
                 intel_cpu_transcoder_set_m_n(intel_crtc,
-                                             &intel_crtc->config.fdi_m_n);
+                                     &intel_crtc->config.fdi_m_n, NULL);
         }
 
         ironlake_set_pipeconf(crtc);
@@ -4093,7 +4093,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 
         if (intel_crtc->config.has_pch_encoder) {
                 intel_cpu_transcoder_set_m_n(intel_crtc,
-                                             &intel_crtc->config.fdi_m_n);
+                                     &intel_crtc->config.fdi_m_n, NULL);
         }
 
         haswell_set_pipeconf(crtc);
@@ -5509,7 +5509,8 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
 }
 
 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
-                                         struct intel_link_m_n *m_n)
+                                         struct intel_link_m_n *m_n,
+                                         struct intel_link_m_n *m2_n2)
 {
         struct drm_device *dev = crtc->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5521,6 +5522,18 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
+                /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
+                 * for gen < 8) and if DRRS is supported (to make sure the
+                 * registers are not unnecessarily accessed).
+                 */
+                if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
+                        crtc->config.has_drrs) {
+                        I915_WRITE(PIPE_DATA_M2(transcoder),
+                                        TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
+                        I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
+                        I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
+                        I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
+                }
         } else {
                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
@@ -5529,12 +5542,13 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
         }
 }
 
-static void intel_dp_set_m_n(struct intel_crtc *crtc)
+void intel_dp_set_m_n(struct intel_crtc *crtc)
 {
         if (crtc->config.has_pch_encoder)
                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
         else
-                intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
+                intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
+                                                   &crtc->config.dp_m2_n2);
 }
 
 static void vlv_update_pll(struct intel_crtc *crtc)