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authorImre Deak <imre.deak@intel.com>2014-04-18 08:55:04 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-05-05 03:09:02 -0400
commitf301b1e116396804c6fcd4a33eb4477a24e0a3b8 (patch)
tree88951418b92155d284d8599cea01a49e469d83b4 /drivers/gpu/drm/i915/intel_display.c
parent51660e0eb6e7130fb1ba511cc1918cbe505be0af (diff)
drm/i915: add missing error capturing of the PIPESTAT reg
While checking the error capture path I noticed that we lacked the power domain-on check for PIPESTAT so fix this by moving that to where the rest of pipe registers are captured. The move also revealed that we actually don't include this register in the error report, so fix that too. v2: - patch introduced in v2 of the patchset v3: - add back !HAS_PCH_SPLIT check (Ville) [ Ignore my previous comment about the gen<=5 || vlv check, I realized that it's the same as !HAS_PCH_SPLIT. ] Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b39d0367dd68..8c852ba02f16 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11911,6 +11911,7 @@ struct intel_display_error_state {
11911 struct intel_pipe_error_state { 11911 struct intel_pipe_error_state {
11912 bool power_domain_on; 11912 bool power_domain_on;
11913 u32 source; 11913 u32 source;
11914 u32 stat;
11914 } pipe[I915_MAX_PIPES]; 11915 } pipe[I915_MAX_PIPES];
11915 11916
11916 struct intel_plane_error_state { 11917 struct intel_plane_error_state {
@@ -11992,6 +11993,9 @@ intel_display_capture_error_state(struct drm_device *dev)
11992 } 11993 }
11993 11994
11994 error->pipe[i].source = I915_READ(PIPESRC(i)); 11995 error->pipe[i].source = I915_READ(PIPESRC(i));
11996
11997 if (!HAS_PCH_SPLIT(dev))
11998 error->pipe[i].stat = I915_READ(PIPESTAT(i));
11995 } 11999 }
11996 12000
11997 error->num_transcoders = INTEL_INFO(dev)->num_pipes; 12001 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
@@ -12042,6 +12046,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12042 err_printf(m, " Power: %s\n", 12046 err_printf(m, " Power: %s\n",
12043 error->pipe[i].power_domain_on ? "on" : "off"); 12047 error->pipe[i].power_domain_on ? "on" : "off");
12044 err_printf(m, " SRC: %08x\n", error->pipe[i].source); 12048 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
12049 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
12045 12050
12046 err_printf(m, "Plane [%d]:\n", i); 12051 err_printf(m, "Plane [%d]:\n", i);
12047 err_printf(m, " CNTR: %08x\n", error->plane[i].control); 12052 err_printf(m, " CNTR: %08x\n", error->plane[i].control);