drm/i915: Use correct pipe config to update pll dividers. V2

Use the new pipe config values to calculate the updated pll dividers.

This regression was introduced in

commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59
Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Date:   Wed Oct 29 11:32:33 2014 +0200

    drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs

	and

	commit 00d958817dd3daaa452c221387ddaf23d1e4c06f
	Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
	Date:   Wed Oct 29 11:32:36 2014 +0200

	    drm/i915: Covert remaining platforms to choose DPLLS before disabling CRTCs

v2: Use intel_pipe_will_have_type() to look at new configuration - Ander

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Tested-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 6 insertions, 6 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ea607f340c76..9480a6173d78 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5733,24 +5733,24 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
         u32 fp, fp2 = 0;
 
         if (IS_PINEVIEW(dev)) {
-                fp = pnv_dpll_compute_fp(&crtc->config.dpll);
+                fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
                 if (reduced_clock)
                         fp2 = pnv_dpll_compute_fp(reduced_clock);
         } else {
-                fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
+                fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
                 if (reduced_clock)
                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
         }
 
-        crtc->config.dpll_hw_state.fp0 = fp;
+        crtc->new_config->dpll_hw_state.fp0 = fp;
 
         crtc->lowfreq_avail = false;
-        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
+        if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
             reduced_clock && i915.powersave) {
-                crtc->config.dpll_hw_state.fp1 = fp2;
+                crtc->new_config->dpll_hw_state.fp1 = fp2;
                 crtc->lowfreq_avail = true;
         } else {
-                crtc->config.dpll_hw_state.fp1 = fp;
+                crtc->new_config->dpll_hw_state.fp1 = fp;
         }
 }