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authorAdam Jackson <ajax@redhat.com>2010-06-25 15:32:14 -0400
committerEric Anholt <eric@anholt.net>2010-08-01 22:03:47 -0400
commite1a4474349997d722e4ae64e40a68feb25307109 (patch)
treef64a7a642aceceec29abe8a393f6eea55fd7dec7 /drivers/gpu/drm/i915/intel_display.c
parent2991196fbc19f68206eb81694e9ef338366ebc53 (diff)
drm/i915/pch: Cosmetic fix to FDI link training
Unmask the bits for link training reporting before starting link training. If stage 1 training finished before we unmask them, then we'd spin around in a loop a few times until smashing on through. Which is harmless, since training _did_ succeed, it just looks ugly in dmesg. Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c58
1 files changed, 24 insertions, 34 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7e57eaba5e25..f67c74a25264 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1604,6 +1604,15 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1604 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR; 1604 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1605 u32 temp, tries = 0; 1605 u32 temp, tries = 0;
1606 1606
1607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1608 for train result */
1609 temp = I915_READ(fdi_rx_imr_reg);
1610 temp &= ~FDI_RX_SYMBOL_LOCK;
1611 temp &= ~FDI_RX_BIT_LOCK;
1612 I915_WRITE(fdi_rx_imr_reg, temp);
1613 I915_READ(fdi_rx_imr_reg);
1614 udelay(150);
1615
1607 /* enable CPU FDI TX and PCH FDI RX */ 1616 /* enable CPU FDI TX and PCH FDI RX */
1608 temp = I915_READ(fdi_tx_reg); 1617 temp = I915_READ(fdi_tx_reg);
1609 temp |= FDI_TX_ENABLE; 1618 temp |= FDI_TX_ENABLE;
@@ -1621,16 +1630,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1621 I915_READ(fdi_rx_reg); 1630 I915_READ(fdi_rx_reg);
1622 udelay(150); 1631 udelay(150);
1623 1632
1624 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 1633 for (tries = 0; tries < 5; tries++) {
1625 for train result */
1626 temp = I915_READ(fdi_rx_imr_reg);
1627 temp &= ~FDI_RX_SYMBOL_LOCK;
1628 temp &= ~FDI_RX_BIT_LOCK;
1629 I915_WRITE(fdi_rx_imr_reg, temp);
1630 I915_READ(fdi_rx_imr_reg);
1631 udelay(150);
1632
1633 for (;;) {
1634 temp = I915_READ(fdi_rx_iir_reg); 1634 temp = I915_READ(fdi_rx_iir_reg);
1635 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 1635 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1636 1636
@@ -1640,14 +1640,9 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1640 temp | FDI_RX_BIT_LOCK); 1640 temp | FDI_RX_BIT_LOCK);
1641 break; 1641 break;
1642 } 1642 }
1643
1644 tries++;
1645
1646 if (tries > 5) {
1647 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1648 break;
1649 }
1650 } 1643 }
1644 if (tries == 5)
1645 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1651 1646
1652 /* Train 2 */ 1647 /* Train 2 */
1653 temp = I915_READ(fdi_tx_reg); 1648 temp = I915_READ(fdi_tx_reg);
@@ -1663,7 +1658,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1663 1658
1664 tries = 0; 1659 tries = 0;
1665 1660
1666 for (;;) { 1661 for (tries = 0; tries < 5; tries++) {
1667 temp = I915_READ(fdi_rx_iir_reg); 1662 temp = I915_READ(fdi_rx_iir_reg);
1668 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 1663 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1669 1664
@@ -1673,14 +1668,9 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1673 DRM_DEBUG_KMS("FDI train 2 done.\n"); 1668 DRM_DEBUG_KMS("FDI train 2 done.\n");
1674 break; 1669 break;
1675 } 1670 }
1676
1677 tries++;
1678
1679 if (tries > 5) {
1680 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1681 break;
1682 }
1683 } 1671 }
1672 if (tries == 5)
1673 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1684 1674
1685 DRM_DEBUG_KMS("FDI train done\n"); 1675 DRM_DEBUG_KMS("FDI train done\n");
1686} 1676}
@@ -1705,6 +1695,15 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
1705 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR; 1695 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1706 u32 temp, i; 1696 u32 temp, i;
1707 1697
1698 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1699 for train result */
1700 temp = I915_READ(fdi_rx_imr_reg);
1701 temp &= ~FDI_RX_SYMBOL_LOCK;
1702 temp &= ~FDI_RX_BIT_LOCK;
1703 I915_WRITE(fdi_rx_imr_reg, temp);
1704 I915_READ(fdi_rx_imr_reg);
1705 udelay(150);
1706
1708 /* enable CPU FDI TX and PCH FDI RX */ 1707 /* enable CPU FDI TX and PCH FDI RX */
1709 temp = I915_READ(fdi_tx_reg); 1708 temp = I915_READ(fdi_tx_reg);
1710 temp |= FDI_TX_ENABLE; 1709 temp |= FDI_TX_ENABLE;
@@ -1730,15 +1729,6 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
1730 I915_READ(fdi_rx_reg); 1729 I915_READ(fdi_rx_reg);
1731 udelay(150); 1730 udelay(150);
1732 1731
1733 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1734 for train result */
1735 temp = I915_READ(fdi_rx_imr_reg);
1736 temp &= ~FDI_RX_SYMBOL_LOCK;
1737 temp &= ~FDI_RX_BIT_LOCK;
1738 I915_WRITE(fdi_rx_imr_reg, temp);
1739 I915_READ(fdi_rx_imr_reg);
1740 udelay(150);
1741
1742 for (i = 0; i < 4; i++ ) { 1732 for (i = 0; i < 4; i++ ) {
1743 temp = I915_READ(fdi_tx_reg); 1733 temp = I915_READ(fdi_tx_reg);
1744 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 1734 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;