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authorJesse Barnes <jbarnes@virtuousgeek.org>2011-01-04 18:09:35 -0500
committerChris Wilson <chris@chris-wilson.co.uk>2011-01-19 07:37:03 -0500
commitd9b6cb568bc6eca8db88357bf8bbb92d42a91b1e (patch)
tree3f2606113a772c80adbf815619bcc310f0ca794e /drivers/gpu/drm/i915/intel_display.c
parent92f2584a083986c05fc811bbdf380c3fa7c12296 (diff)
drm/i915: assert panel is unlocked before writing transcoder timing regs
Otherwise our writes will be silently ignored. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 515e0b99f32e..f274d5b1b7c6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2444,7 +2444,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
2444 I915_WRITE(PCH_DPLL_SEL, temp); 2444 I915_WRITE(PCH_DPLL_SEL, temp);
2445 } 2445 }
2446 2446
2447 /* set transcoder timing */ 2447 /* set transcoder timing, panel must allow it */
2448 assert_panel_unlocked(dev_priv, pipe);
2448 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); 2449 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2449 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); 2450 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2450 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); 2451 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));