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authorImre Deak <imre.deak@intel.com>2015-03-17 05:40:03 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-03-20 06:48:20 -0400
commitd5dd62bd9a19bcea4bcf20f66de56591fdd0d8d2 (patch)
treea05c4a6f880456d54f7fb305f83eb84dd5c554b2 /drivers/gpu/drm/i915/intel_display.c
parentbdd7554d568fa165b0e86fc32b1cde3c895ff774 (diff)
drm/i915: factor out vlv_PLL_is_optimal
Factor out the logic to decide whether the newly calculated dividers are better than the best found so far. Do this for clarity and to prepare for the upcoming BXT helper needing the same. No functional change. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c50
1 files changed, 36 insertions, 14 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3c91bd19987b..9dc9a85d0008 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -776,6 +776,33 @@ g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
776 return found; 776 return found;
777} 777}
778 778
779/*
780 * Check if the calculated PLL configuration is more optimal compared to the
781 * best configuration and error found so far. Return the calculated error.
782 */
783static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
784 const intel_clock_t *calculated_clock,
785 const intel_clock_t *best_clock,
786 unsigned int best_error_ppm,
787 unsigned int *error_ppm)
788{
789 *error_ppm = div_u64(1000000ULL *
790 abs(target_freq - calculated_clock->dot),
791 target_freq);
792 /*
793 * Prefer a better P value over a better (smaller) error if the error
794 * is small. Ensure this preference for future configurations too by
795 * setting the error to 0.
796 */
797 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
798 *error_ppm = 0;
799
800 return true;
801 }
802
803 return *error_ppm + 10 < best_error_ppm;
804}
805
779static bool 806static bool
780vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, 807vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
781 int target, int refclk, intel_clock_t *match_clock, 808 int target, int refclk, intel_clock_t *match_clock,
@@ -800,7 +827,7 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
800 clock.p = clock.p1 * clock.p2; 827 clock.p = clock.p1 * clock.p2;
801 /* based on hardware requirement, prefer bigger m1,m2 values */ 828 /* based on hardware requirement, prefer bigger m1,m2 values */
802 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 829 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
803 unsigned int ppm, diff; 830 unsigned int ppm;
804 831
805 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, 832 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
806 refclk * clock.m1); 833 refclk * clock.m1);
@@ -811,20 +838,15 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
811 &clock)) 838 &clock))
812 continue; 839 continue;
813 840
814 diff = abs(clock.dot - target); 841 if (!vlv_PLL_is_optimal(dev, target,
815 ppm = div_u64(1000000ULL * diff, target); 842 &clock,
816 843 best_clock,
817 if (ppm < 100 && clock.p > best_clock->p) { 844 bestppm, &ppm))
818 bestppm = 0; 845 continue;
819 *best_clock = clock;
820 found = true;
821 }
822 846
823 if (bestppm >= 10 && ppm < bestppm - 10) { 847 *best_clock = clock;
824 bestppm = ppm; 848 bestppm = ppm;
825 *best_clock = clock; 849 found = true;
826 found = true;
827 }
828 } 850 }
829 } 851 }
830 } 852 }