aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_display.c
diff options
context:
space:
mode:
authorVille Syrjälä <ville.syrjala@linux.intel.com>2014-06-13 06:37:49 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-07-07 05:23:21 -0400
commitd197b7d3480b5c9a3c33b224684fa942d76d1e59 (patch)
tree47b817cbf4df6ef92db97dad7261271e5142ba7e /drivers/gpu/drm/i915/intel_display.c
parent9cf33db5eb6a485a16668e19dbcfdfc0f6c61090 (diff)
drm/i915: Move vlv cdclk code to .get_display_clock_speed()
We have a standard hook for reading out the current cdclk. Move the VLV code from valleyview_cur_cdclk() to .get_display_clock_speed(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c33
1 files changed, 13 insertions, 20 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3feaaba3616d..310218afe9c9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4485,7 +4485,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4485 struct drm_i915_private *dev_priv = dev->dev_private; 4485 struct drm_i915_private *dev_priv = dev->dev_private;
4486 u32 val, cmd; 4486 u32 val, cmd;
4487 4487
4488 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq); 4488 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4489 dev_priv->vlv_cdclk_freq = cdclk; 4489 dev_priv->vlv_cdclk_freq = cdclk;
4490 4490
4491 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 4491 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
@@ -4542,24 +4542,6 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4542 intel_i2c_reset(dev); 4542 intel_i2c_reset(dev);
4543} 4543}
4544 4544
4545int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4546{
4547 int cur_cdclk, vco;
4548 int divider;
4549
4550 vco = valleyview_get_vco(dev_priv);
4551
4552 mutex_lock(&dev_priv->dpio_lock);
4553 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4554 mutex_unlock(&dev_priv->dpio_lock);
4555
4556 divider &= DISPLAY_FREQUENCY_VALUES;
4557
4558 cur_cdclk = DIV_ROUND_CLOSEST(vco << 1, divider + 1);
4559
4560 return cur_cdclk;
4561}
4562
4563static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, 4545static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4564 int max_pixclk) 4546 int max_pixclk)
4565{ 4547{
@@ -5269,7 +5251,18 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
5269 5251
5270static int valleyview_get_display_clock_speed(struct drm_device *dev) 5252static int valleyview_get_display_clock_speed(struct drm_device *dev)
5271{ 5253{
5272 return 400000; /* FIXME */ 5254 struct drm_i915_private *dev_priv = dev->dev_private;
5255 int vco = valleyview_get_vco(dev_priv);
5256 u32 val;
5257 int divider;
5258
5259 mutex_lock(&dev_priv->dpio_lock);
5260 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5261 mutex_unlock(&dev_priv->dpio_lock);
5262
5263 divider = val & DISPLAY_FREQUENCY_VALUES;
5264
5265 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5273} 5266}
5274 5267
5275static int i945_get_display_clock_speed(struct drm_device *dev) 5268static int i945_get_display_clock_speed(struct drm_device *dev)