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authorChris Wilson <chris@chris-wilson.co.uk>2011-02-21 09:43:56 -0500
committerChris Wilson <chris@chris-wilson.co.uk>2011-02-22 10:56:25 -0500
commitce453d81cb0397aa7d5148984f51907e14072d74 (patch)
tree28545a19bf61f047671d17c96d33643a83f3c43c /drivers/gpu/drm/i915/intel_display.c
parent8408c282f0cf34ee166df5f842f2861d245407fd (diff)
drm/i915: Use a device flag for non-interruptible phases
The code paths for modesetting are growing in complexity as we may need to move the buffers around in order to fit the scanout in the aperture. Therefore we face a choice as to whether to thread the interruptible status through the entire pinning and unbinding code paths or to add a flag to the device when we may not be interrupted by a signal. This does the latter and so fixes a few instances of modesetting failures under stress. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 40fcbc91139c..c19e974c0019 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2067,6 +2067,7 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
2067 struct drm_i915_gem_object *obj, 2067 struct drm_i915_gem_object *obj,
2068 struct intel_ring_buffer *pipelined) 2068 struct intel_ring_buffer *pipelined)
2069{ 2069{
2070 struct drm_i915_private *dev_priv = dev->dev_private;
2070 u32 alignment; 2071 u32 alignment;
2071 int ret; 2072 int ret;
2072 2073
@@ -2091,9 +2092,10 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
2091 BUG(); 2092 BUG();
2092 } 2093 }
2093 2094
2095 dev_priv->mm.interruptible = false;
2094 ret = i915_gem_object_pin(obj, alignment, true); 2096 ret = i915_gem_object_pin(obj, alignment, true);
2095 if (ret) 2097 if (ret)
2096 return ret; 2098 goto err_interruptible;
2097 2099
2098 ret = i915_gem_object_set_to_display_plane(obj, pipelined); 2100 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
2099 if (ret) 2101 if (ret)
@@ -2105,15 +2107,18 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
2105 * a fence as the cost is not that onerous. 2107 * a fence as the cost is not that onerous.
2106 */ 2108 */
2107 if (obj->tiling_mode != I915_TILING_NONE) { 2109 if (obj->tiling_mode != I915_TILING_NONE) {
2108 ret = i915_gem_object_get_fence(obj, pipelined, false); 2110 ret = i915_gem_object_get_fence(obj, pipelined);
2109 if (ret) 2111 if (ret)
2110 goto err_unpin; 2112 goto err_unpin;
2111 } 2113 }
2112 2114
2115 dev_priv->mm.interruptible = true;
2113 return 0; 2116 return 0;
2114 2117
2115err_unpin: 2118err_unpin:
2116 i915_gem_object_unpin(obj); 2119 i915_gem_object_unpin(obj);
2120err_interruptible:
2121 dev_priv->mm.interruptible = true;
2117 return ret; 2122 return ret;
2118} 2123}
2119 2124
@@ -2247,7 +2252,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2247 * This should only fail upon a hung GPU, in which case we 2252 * This should only fail upon a hung GPU, in which case we
2248 * can safely continue. 2253 * can safely continue.
2249 */ 2254 */
2250 ret = i915_gem_object_flush_gpu(obj, false); 2255 ret = i915_gem_object_flush_gpu(obj);
2251 (void) ret; 2256 (void) ret;
2252 } 2257 }
2253 2258
@@ -2994,9 +2999,12 @@ static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2994{ 2999{
2995 if (!enable && intel_crtc->overlay) { 3000 if (!enable && intel_crtc->overlay) {
2996 struct drm_device *dev = intel_crtc->base.dev; 3001 struct drm_device *dev = intel_crtc->base.dev;
3002 struct drm_i915_private *dev_priv = dev->dev_private;
2997 3003
2998 mutex_lock(&dev->struct_mutex); 3004 mutex_lock(&dev->struct_mutex);
2999 (void) intel_overlay_switch_off(intel_crtc->overlay, false); 3005 dev_priv->mm.interruptible = false;
3006 (void) intel_overlay_switch_off(intel_crtc->overlay);
3007 dev_priv->mm.interruptible = true;
3000 mutex_unlock(&dev->struct_mutex); 3008 mutex_unlock(&dev->struct_mutex);
3001 } 3009 }
3002 3010