diff options
author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-06-27 13:47:19 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-07-01 05:28:01 -0400 |
commit | c93f54cf7de31d44b4036d0d1e291172b2bd5743 (patch) | |
tree | f71fd4b712aa00c236868b94d0d397eaa92638a3 /drivers/gpu/drm/i915/intel_display.c | |
parent | 911bdf0ae6405db3313c6e5798cf08640fdd0714 (diff) |
drm/i915: pixel multiplier readout support for pch ports
Now that we painstakingly track the shared pch dplls we can finally
implement pixel mutliplier readout support for pch ports, too.
v2: Undo the temporary hack to disable the sdvo pixel multiplier
cross-checking.
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 112120e909ee..65e8f5e512d2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -5815,10 +5815,6 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, | |||
5815 | 5815 | ||
5816 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | 5816 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
5817 | 5817 | ||
5818 | /* XXX: Can't properly read out the pch dpll pixel multiplier | ||
5819 | * since we don't have state tracking for pch clocks yet. */ | ||
5820 | pipe_config->pixel_multiplier = 1; | ||
5821 | |||
5822 | if (HAS_PCH_IBX(dev_priv->dev)) { | 5818 | if (HAS_PCH_IBX(dev_priv->dev)) { |
5823 | pipe_config->shared_dpll = crtc->pipe; | 5819 | pipe_config->shared_dpll = crtc->pipe; |
5824 | } else { | 5820 | } else { |
@@ -5833,6 +5829,11 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, | |||
5833 | 5829 | ||
5834 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | 5830 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
5835 | &pipe_config->dpll_hw_state)); | 5831 | &pipe_config->dpll_hw_state)); |
5832 | |||
5833 | tmp = pipe_config->dpll_hw_state.dpll; | ||
5834 | pipe_config->pixel_multiplier = | ||
5835 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | ||
5836 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | ||
5836 | } else { | 5837 | } else { |
5837 | pipe_config->pixel_multiplier = 1; | 5838 | pipe_config->pixel_multiplier = 1; |
5838 | } | 5839 | } |
@@ -8083,8 +8084,7 @@ intel_pipe_config_compare(struct drm_device *dev, | |||
8083 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | 8084 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); |
8084 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | 8085 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); |
8085 | 8086 | ||
8086 | if (!HAS_PCH_SPLIT(dev)) | 8087 | PIPE_CONF_CHECK_I(pixel_multiplier); |
8087 | PIPE_CONF_CHECK_I(pixel_multiplier); | ||
8088 | 8088 | ||
8089 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | 8089 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8090 | DRM_MODE_FLAG_INTERLACE); | 8090 | DRM_MODE_FLAG_INTERLACE); |