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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2012-10-31 16:12:45 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-11-11 17:51:22 -0500
commita35f267946947b3798827a783d82d3d2aa55697d (patch)
tree059914c16cd764a99ddcc7d1df7589946e0252a0 /drivers/gpu/drm/i915/intel_display.c
parent25e78e90f33a783e8129e29c1a567a63300ca8ce (diff)
drm/i915: remove IBX code from lpt_enable_pch_transcoder
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c15
1 files changed, 1 insertions, 14 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9c5783cc69dd..2de9a6e4b5fd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1744,22 +1744,9 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1744 val = I915_READ(reg); 1744 val = I915_READ(reg);
1745 pipeconf_val = I915_READ(PIPECONF(pipe)); 1745 pipeconf_val = I915_READ(PIPECONF(pipe));
1746 1746
1747 if (HAS_PCH_IBX(dev_priv->dev)) {
1748 /*
1749 * make the BPC in transcoder be consistent with
1750 * that in pipeconf reg.
1751 */
1752 val &= ~PIPE_BPC_MASK;
1753 val |= pipeconf_val & PIPE_BPC_MASK;
1754 }
1755
1756 val &= ~TRANS_INTERLACE_MASK; 1747 val &= ~TRANS_INTERLACE_MASK;
1757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) 1748 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1758 if (HAS_PCH_IBX(dev_priv->dev) && 1749 val |= TRANS_INTERLACED;
1759 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1760 val |= TRANS_LEGACY_INTERLACED_ILK;
1761 else
1762 val |= TRANS_INTERLACED;
1763 else 1750 else
1764 val |= TRANS_PROGRESSIVE; 1751 val |= TRANS_PROGRESSIVE;
1765 1752