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authorBen Widawsky <ben@bwidawsk.net>2012-04-14 21:41:32 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-04-18 05:19:05 -0400
commita1e969e0332de7a430e62822cee8f2ec8d83cd7c (patch)
tree8bf72c6ac78fae6793e46c178b690d5461804135 /drivers/gpu/drm/i915/intel_display.c
parent65f5687603ea6ede1cb01b3d6c16a8c1fac88541 (diff)
drm/i915: [GEN7] Use HW scheduler for fixed function shaders
This originally started as a patch from Bernard as a way of simply setting the VS scheduler. After submitting the RFC patch, we decided to also modify the DS scheduler. To be most explicit, I've made the patch explicitly set all scheduler modes, and included the defines for other modes (in case someone feels frisky later). The rest of the story gets a bit weird. The first version of the patch showed an almost unbelievable performance improvement. Since rebasing my branch it appears the performance improvement has gone, unfortunately. But setting these bits seem to be the right thing to do given that the docs describe corruption that can occur with the default settings. In summary, I am seeing no more perf improvements (or regressions) in my limited testing, but we believe this should be set to prevent rendering corruption, therefore cc stable. v1: Clear bit 4 also (Ken + Eugeni) Do a full clear + set of the bits we want (Me). Cc: Bernard Kilarski <bernard.r.kilarski@intel.com> Cc: stable <stable@vger.kernel.org> Reviewed-by (RFC): Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 78179e03a901..96fc4679d438 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8937,6 +8937,18 @@ static void gen6_init_clock_gating(struct drm_device *dev)
8937 } 8937 }
8938} 8938}
8939 8939
8940static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
8941{
8942 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
8943
8944 reg &= ~GEN7_FF_SCHED_MASK;
8945 reg |= GEN7_FF_TS_SCHED_HW;
8946 reg |= GEN7_FF_VS_SCHED_HW;
8947 reg |= GEN7_FF_DS_SCHED_HW;
8948
8949 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
8950}
8951
8940static void ivybridge_init_clock_gating(struct drm_device *dev) 8952static void ivybridge_init_clock_gating(struct drm_device *dev)
8941{ 8953{
8942 struct drm_i915_private *dev_priv = dev->dev_private; 8954 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8981,6 +8993,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
8981 DISPPLANE_TRICKLE_FEED_DISABLE); 8993 DISPPLANE_TRICKLE_FEED_DISABLE);
8982 intel_flush_display_plane(dev_priv, pipe); 8994 intel_flush_display_plane(dev_priv, pipe);
8983 } 8995 }
8996
8997 gen7_setup_fixed_func_scheduler(dev_priv);
8984} 8998}
8985 8999
8986static void valleyview_init_clock_gating(struct drm_device *dev) 9000static void valleyview_init_clock_gating(struct drm_device *dev)