drm/i915: fix D_COMP usage on BDW

On HSW, the D_COMP register can be accessed through the mailbox (read
and write) or through MMIO on a MCHBAR offset (read only). On BDW, the
access should be done through MMIO on another address. So to account
for all these cases, create hsw_read_dcomp() with the correct
implementation for reading, and also fix hsw_write_dcomp() to do the
correct thing on BDW.

With this patch, we can now get back from the PC8+ state on BDW. We
were previously getting a black screen and lots of dmesg errors.
Please notice that the bug only happens when you actually reach the
PC8+ states, not when you only allow it.

Testcase: igt/pm_rpm/rte
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 16 insertions, 5 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index aea48715aa1e..34286c695bcf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7339,6 +7339,16 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
 }
 
+static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
+{
+        struct drm_device *dev = dev_priv->dev;
+
+        if (IS_HASWELL(dev))
+                return I915_READ(D_COMP_HSW);
+        else
+                return I915_READ(D_COMP_BDW);
+}
+
 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
 {
         struct drm_device *dev = dev_priv->dev;
@@ -7350,9 +7360,9 @@ static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
                         DRM_ERROR("Failed to write to D_COMP\n");
                 mutex_unlock(&dev_priv->rps.hw_lock);
         } else {
-                I915_WRITE(D_COMP, val);
+                I915_WRITE(D_COMP_BDW, val);
+                POSTING_READ(D_COMP_BDW);
         }
-        POSTING_READ(D_COMP);
 }
 
 /*
@@ -7390,12 +7400,13 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
                 DRM_ERROR("LCPLL still locked\n");
 
-        val = I915_READ(D_COMP);
+        val = hsw_read_dcomp(dev_priv);
         val |= D_COMP_COMP_DISABLE;
         hsw_write_dcomp(dev_priv, val);
         ndelay(100);
 
-        if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
+        if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
+                     1))
                 DRM_ERROR("D_COMP RCOMP still in progress\n");
 
         if (allow_power_down) {
@@ -7444,7 +7455,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
                 POSTING_READ(LCPLL_CTL);
         }
 
-        val = I915_READ(D_COMP);
+        val = hsw_read_dcomp(dev_priv);
         val |= D_COMP_COMP_FORCE;
         val &= ~D_COMP_COMP_DISABLE;
         hsw_write_dcomp(dev_priv, val);