drm/i915: Update prop, int co-eff and gain threshold for CHV

This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.

v2: Split the original changes into multiple smaller patches based on
review by Ville

v3: Addressed Ville's review comments. Fixed the error introduced in v2.
Clear the old bits before we modify those bits as part of RMW.

v4: TDC target cnt is 10 bits and not 8 bits (Ville)

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 31 insertions, 12 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2eea258e5865..cbf426ec92e3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6159,10 +6159,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
         int pipe = crtc->pipe;
         int dpll_reg = DPLL(crtc->pipe);
         enum dpio_channel port = vlv_pipe_to_channel(pipe);
-        u32 loopfilter, intcoeff;
+        u32 loopfilter, tribuf_calcntr;
         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
         u32 dpio_val;
-        int refclk;
+        int vco;
 
         bestn = pipe_config->dpll.n;
         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
@@ -6170,7 +6170,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
         bestm2 = pipe_config->dpll.m2 >> 22;
         bestp1 = pipe_config->dpll.p1;
         bestp2 = pipe_config->dpll.p2;
+        vco = pipe_config->dpll.vco;
         dpio_val = 0;
+        loopfilter = 0;
 
         /*
          * Enable Refclk and SSC
@@ -6217,18 +6219,35 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
 
         /* Loop filter */
-        refclk = i9xx_get_refclk(crtc, 0);
-        loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
-                2 << DPIO_CHV_GAIN_CTRL_SHIFT;
-        if (refclk == 100000)
-                intcoeff = 11;
-        else if (refclk == 38400)
-                intcoeff = 10;
-        else
-                intcoeff = 9;
-        loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
+        if (vco == 5400000) {
+                loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
+                loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
+                loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
+                tribuf_calcntr = 0x9;
+        } else if (vco <= 6200000) {
+                loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
+                loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
+                loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+                tribuf_calcntr = 0x9;
+        } else if (vco <= 6480000) {
+                loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+                loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+                loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+                tribuf_calcntr = 0x8;
+        } else {
+                /* Not supported. Apply the same limits as in the max case */
+                loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+                loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+                loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+                tribuf_calcntr = 0;
+        }
         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
 
+        dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
+        dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
+        dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
+        vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
+
         /* AFC Recal */
         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |