drm/i915: Read CHV_PLL_DW8 from the correct offset

We accidentally pass 'pipe' instead of 'port' to CHV_PLL_DW8() and
with PIPE_C we end up at register offset 0x8320 which isn't the
0x8020 we wanted. Fix it.

The problem was fortunately caught by the sanity check in vlv_dpio_read():
WARNING: CPU: 1 PID: 238 at ../drivers/gpu/drm/i915/intel_sideband.c:200 vlv_dpio_read+0x77/0x80 [i915]()
DPIO read pipe C reg 0x8320 == 0xffffffff

The problem got introduced with this commit:
 commit 71af07f91f12bbab96335e202c82525d31680960
 Author: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
 Date:   Thu Mar 5 19:33:08 2015 +0530

    drm/i915: Update prop, int co-eff and gain threshold for CHV

Cc: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Todd Previte <tprevite@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8d1925404383..10af910c3d26 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6246,7 +6246,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
         }
         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
 
-        dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
+        dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);