diff options
author | Imre Deak <imre.deak@intel.com> | 2014-03-05 09:20:52 -0500 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-03-07 16:36:46 -0500 |
commit | 77d22dcacddb929bc700370d0fc079447c47fd89 (patch) | |
tree | 016a5205e336b7af38784f40677a9ad7d1d39ee5 /drivers/gpu/drm/i915/intel_display.c | |
parent | 70bf407c8deb5d2e26468a99f1af19a166bb89e7 (diff) |
drm/i915: move modeset_update_power_wells earlier
These functions will be needed by the valleyview specific power well
update functionality added in an upcoming patch, so move them earlier.
No functional change.
v2:
- no change
v3:
- rebase on latest -nightly
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 140 |
1 files changed, 70 insertions, 70 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 91c2e3b06396..ee786c585026 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -3958,6 +3958,76 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc) | |||
3958 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | 3958 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
3959 | } | 3959 | } |
3960 | 3960 | ||
3961 | #define for_each_power_domain(domain, mask) \ | ||
3962 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | ||
3963 | if ((1 << (domain)) & (mask)) | ||
3964 | |||
3965 | static unsigned long get_pipe_power_domains(struct drm_device *dev, | ||
3966 | enum pipe pipe, bool pfit_enabled) | ||
3967 | { | ||
3968 | unsigned long mask; | ||
3969 | enum transcoder transcoder; | ||
3970 | |||
3971 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | ||
3972 | |||
3973 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | ||
3974 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | ||
3975 | if (pfit_enabled) | ||
3976 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | ||
3977 | |||
3978 | return mask; | ||
3979 | } | ||
3980 | |||
3981 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, | ||
3982 | bool enable) | ||
3983 | { | ||
3984 | if (dev_priv->power_domains.init_power_on == enable) | ||
3985 | return; | ||
3986 | |||
3987 | if (enable) | ||
3988 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | ||
3989 | else | ||
3990 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | ||
3991 | |||
3992 | dev_priv->power_domains.init_power_on = enable; | ||
3993 | } | ||
3994 | |||
3995 | static void modeset_update_crtc_power_domains(struct drm_device *dev) | ||
3996 | { | ||
3997 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
3998 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | ||
3999 | struct intel_crtc *crtc; | ||
4000 | |||
4001 | /* | ||
4002 | * First get all needed power domains, then put all unneeded, to avoid | ||
4003 | * any unnecessary toggling of the power wells. | ||
4004 | */ | ||
4005 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | ||
4006 | enum intel_display_power_domain domain; | ||
4007 | |||
4008 | if (!crtc->base.enabled) | ||
4009 | continue; | ||
4010 | |||
4011 | pipe_domains[crtc->pipe] = get_pipe_power_domains(dev, | ||
4012 | crtc->pipe, | ||
4013 | crtc->config.pch_pfit.enabled); | ||
4014 | |||
4015 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | ||
4016 | intel_display_power_get(dev_priv, domain); | ||
4017 | } | ||
4018 | |||
4019 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | ||
4020 | enum intel_display_power_domain domain; | ||
4021 | |||
4022 | for_each_power_domain(domain, crtc->enabled_power_domains) | ||
4023 | intel_display_power_put(dev_priv, domain); | ||
4024 | |||
4025 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | ||
4026 | } | ||
4027 | |||
4028 | intel_display_set_init_power(dev_priv, false); | ||
4029 | } | ||
4030 | |||
3961 | int valleyview_get_vco(struct drm_i915_private *dev_priv) | 4031 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
3962 | { | 4032 | { |
3963 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | 4033 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
@@ -6817,76 +6887,6 @@ done: | |||
6817 | mutex_unlock(&dev_priv->pc8.lock); | 6887 | mutex_unlock(&dev_priv->pc8.lock); |
6818 | } | 6888 | } |
6819 | 6889 | ||
6820 | #define for_each_power_domain(domain, mask) \ | ||
6821 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | ||
6822 | if ((1 << (domain)) & (mask)) | ||
6823 | |||
6824 | static unsigned long get_pipe_power_domains(struct drm_device *dev, | ||
6825 | enum pipe pipe, bool pfit_enabled) | ||
6826 | { | ||
6827 | unsigned long mask; | ||
6828 | enum transcoder transcoder; | ||
6829 | |||
6830 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | ||
6831 | |||
6832 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | ||
6833 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | ||
6834 | if (pfit_enabled) | ||
6835 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | ||
6836 | |||
6837 | return mask; | ||
6838 | } | ||
6839 | |||
6840 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, | ||
6841 | bool enable) | ||
6842 | { | ||
6843 | if (dev_priv->power_domains.init_power_on == enable) | ||
6844 | return; | ||
6845 | |||
6846 | if (enable) | ||
6847 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | ||
6848 | else | ||
6849 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | ||
6850 | |||
6851 | dev_priv->power_domains.init_power_on = enable; | ||
6852 | } | ||
6853 | |||
6854 | static void modeset_update_crtc_power_domains(struct drm_device *dev) | ||
6855 | { | ||
6856 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
6857 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | ||
6858 | struct intel_crtc *crtc; | ||
6859 | |||
6860 | /* | ||
6861 | * First get all needed power domains, then put all unneeded, to avoid | ||
6862 | * any unnecessary toggling of the power wells. | ||
6863 | */ | ||
6864 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | ||
6865 | enum intel_display_power_domain domain; | ||
6866 | |||
6867 | if (!crtc->base.enabled) | ||
6868 | continue; | ||
6869 | |||
6870 | pipe_domains[crtc->pipe] = get_pipe_power_domains(dev, | ||
6871 | crtc->pipe, | ||
6872 | crtc->config.pch_pfit.enabled); | ||
6873 | |||
6874 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | ||
6875 | intel_display_power_get(dev_priv, domain); | ||
6876 | } | ||
6877 | |||
6878 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | ||
6879 | enum intel_display_power_domain domain; | ||
6880 | |||
6881 | for_each_power_domain(domain, crtc->enabled_power_domains) | ||
6882 | intel_display_power_put(dev_priv, domain); | ||
6883 | |||
6884 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | ||
6885 | } | ||
6886 | |||
6887 | intel_display_set_init_power(dev_priv, false); | ||
6888 | } | ||
6889 | |||
6890 | static void haswell_modeset_global_resources(struct drm_device *dev) | 6890 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6891 | { | 6891 | { |
6892 | modeset_update_crtc_power_domains(dev); | 6892 | modeset_update_crtc_power_domains(dev); |