drm/i915: ddi: move pch setup after encoder->pre_enable

This is needed by an upcoming patch that moves the PCH/CRT PLL enabling
into the pre_enable hook, after which we want to keep the modeset
sequence at its current state. At this point this won't have an effect
since the PCH/CRT pre_enable hook is atm a NOP.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 5 insertions, 6 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e1b0049347a6..8ce89c8aa92b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4100,16 +4100,15 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
         intel_crtc->active = true;
 
         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
-        if (intel_crtc->config.has_pch_encoder)
-                intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
-
-        if (intel_crtc->config.has_pch_encoder)
-                dev_priv->display.fdi_link_train(crtc);
-
         for_each_encoder_on_crtc(dev, crtc, encoder)
                 if (encoder->pre_enable)
                         encoder->pre_enable(encoder);
 
+        if (intel_crtc->config.has_pch_encoder) {
+                intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
+                dev_priv->display.fdi_link_train(crtc);
+        }
+
         intel_ddi_enable_pipe_clock(intel_crtc);
 
         ironlake_pfit_enable(intel_crtc);