diff options
author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-01-16 14:57:54 -0500 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-01-21 11:13:05 -0500 |
commit | 47842649ef43ba4b81ac2486df8caa0934e01195 (patch) | |
tree | dac8890f47c184c2b5441b9de1eec0d82a227037 /drivers/gpu/drm/i915/intel_display.c | |
parent | c6a32fcbbbc25d7d4e7178aa984e5ef186ee9589 (diff) |
drm/i915: properly mask and or watermark values for sprites
Now that we're using the sprite WM fields, we need to take care not to
clobber them in the main update_wm functions. While we're at it, make
sure we mask out the old sprite wm value before or'ing in the new one
when the sprite wm is updated.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 24 |
1 files changed, 17 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4247a7b1823b..ec31350337d3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -4548,6 +4548,7 @@ void sandybridge_update_wm(struct drm_device *dev) | |||
4548 | { | 4548 | { |
4549 | struct drm_i915_private *dev_priv = dev->dev_private; | 4549 | struct drm_i915_private *dev_priv = dev->dev_private; |
4550 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ | 4550 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
4551 | u32 val; | ||
4551 | int fbc_wm, plane_wm, cursor_wm; | 4552 | int fbc_wm, plane_wm, cursor_wm; |
4552 | unsigned int enabled; | 4553 | unsigned int enabled; |
4553 | 4554 | ||
@@ -4556,8 +4557,10 @@ void sandybridge_update_wm(struct drm_device *dev) | |||
4556 | &sandybridge_display_wm_info, latency, | 4557 | &sandybridge_display_wm_info, latency, |
4557 | &sandybridge_cursor_wm_info, latency, | 4558 | &sandybridge_cursor_wm_info, latency, |
4558 | &plane_wm, &cursor_wm)) { | 4559 | &plane_wm, &cursor_wm)) { |
4559 | I915_WRITE(WM0_PIPEA_ILK, | 4560 | val = I915_READ(WM0_PIPEA_ILK); |
4560 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | 4561 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
4562 | I915_WRITE(WM0_PIPEA_ILK, val | | ||
4563 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | ||
4561 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | 4564 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
4562 | " plane %d, " "cursor: %d\n", | 4565 | " plane %d, " "cursor: %d\n", |
4563 | plane_wm, cursor_wm); | 4566 | plane_wm, cursor_wm); |
@@ -4568,8 +4571,10 @@ void sandybridge_update_wm(struct drm_device *dev) | |||
4568 | &sandybridge_display_wm_info, latency, | 4571 | &sandybridge_display_wm_info, latency, |
4569 | &sandybridge_cursor_wm_info, latency, | 4572 | &sandybridge_cursor_wm_info, latency, |
4570 | &plane_wm, &cursor_wm)) { | 4573 | &plane_wm, &cursor_wm)) { |
4571 | I915_WRITE(WM0_PIPEB_ILK, | 4574 | val = I915_READ(WM0_PIPEB_ILK); |
4572 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | 4575 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
4576 | I915_WRITE(WM0_PIPEB_ILK, val | | ||
4577 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | ||
4573 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | 4578 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
4574 | " plane %d, cursor: %d\n", | 4579 | " plane %d, cursor: %d\n", |
4575 | plane_wm, cursor_wm); | 4580 | plane_wm, cursor_wm); |
@@ -4582,8 +4587,10 @@ void sandybridge_update_wm(struct drm_device *dev) | |||
4582 | &sandybridge_display_wm_info, latency, | 4587 | &sandybridge_display_wm_info, latency, |
4583 | &sandybridge_cursor_wm_info, latency, | 4588 | &sandybridge_cursor_wm_info, latency, |
4584 | &plane_wm, &cursor_wm)) { | 4589 | &plane_wm, &cursor_wm)) { |
4585 | I915_WRITE(WM0_PIPEC_IVB, | 4590 | val = I915_READ(WM0_PIPEC_IVB); |
4586 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | 4591 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); |
4592 | I915_WRITE(WM0_PIPEC_IVB, val | | ||
4593 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | ||
4587 | DRM_DEBUG_KMS("FIFO watermarks For pipe C -" | 4594 | DRM_DEBUG_KMS("FIFO watermarks For pipe C -" |
4588 | " plane %d, cursor: %d\n", | 4595 | " plane %d, cursor: %d\n", |
4589 | plane_wm, cursor_wm); | 4596 | plane_wm, cursor_wm); |
@@ -4727,6 +4734,7 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, | |||
4727 | { | 4734 | { |
4728 | struct drm_i915_private *dev_priv = dev->dev_private; | 4735 | struct drm_i915_private *dev_priv = dev->dev_private; |
4729 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ | 4736 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
4737 | u32 val; | ||
4730 | int sprite_wm, reg; | 4738 | int sprite_wm, reg; |
4731 | int ret; | 4739 | int ret; |
4732 | 4740 | ||
@@ -4753,7 +4761,9 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, | |||
4753 | return; | 4761 | return; |
4754 | } | 4762 | } |
4755 | 4763 | ||
4756 | I915_WRITE(reg, I915_READ(reg) | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); | 4764 | val = I915_READ(reg); |
4765 | val &= ~WM0_PIPE_SPRITE_MASK; | ||
4766 | I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); | ||
4757 | DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); | 4767 | DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); |
4758 | 4768 | ||
4759 | 4769 | ||